SynTest Products

RobustScan™ - Framework for Soft-Error Protection
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RobustScan™ provides a platform for users to pick patented Configurable Soft-Error Resilience (CSER) cells or their preferred SER mitigation cells. First, Soft-Error Rate (SER) analysis is performed. Then it performs automatic robust-scan-cell and hardened-combinational-cell selection and synthesis. Finally it generates verification testbenches for the final design. RobustScan™ can be used with scan chains inserted using third-party tools; it can be linked to third-party's SER analysis programs and is fully compatible with SynTest's existing DFT tools for test, debug, and diagnosis.

DFT- PRO Plus ™ - A Comprehensive Package of DFT Tools     view data sheet

DFT-PRO Plus ™ offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and Boundary-Scan Design (BSD) synthesis. The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow. This gives users the freedom to choose any commercially available logic and scan synthesis tools from vendors such as Cadence, Incentia, Mentor, or Synopsys and enables a one-pass RTL to GDSII synthesis flow. It also eases overall design floor planning.

VirtualScan™ and UltraScan™ - Tool Suite for Compression Scan Synthesis and ATPG
  view VirtualScan data sheet   view UltraScan data sheet
VirtualScan™ is SynTest's solution to combat increase in test data volume and test cycle volume. With VirtualScan™ an extremely large number of short scan chains within an SOC can be virtually accessed from outside the chip with a limited number of pins assigned as scan pins. Inside the chip, SynTest's new patent-pending circuitry is used to broadcast each external scan-input chain to a user-selectable number of internal scan chains and at the other end, compact them into the original number of external scan chains. An evaluation on a 2-million gate design using VirtualScan™ showed a 22x reduction in test time. Further, the static and dynamic compaction capabilities of SynTest's powerful ATPG tool help reduce pattern sizes, leading to overall reduction in test costs.

UltraScan™ is SynTest's solution to reduce test time 50x to 500x. It is used along with VirtualScan™ to reduce the overall test cost. UltraScan™ extends life of existing ATE for testing large SOC designs. It reduces test time and data volume for all scan designs with ATPG compression structures offered by VirtualScan™. With UltraScan™ a small number of high-speed I/O pads are sufficient to run a scan ATPG test for a design with a large number of internal scan chains of shorter length. It achieves pin reduction through proprietary TDDM/ TDM circuitry. Overall shorter test load times are realized by taking advantage of the unutilized bandwidth available on high-speed channels on the ATE during low-speed scan-shift operation. UltraScan™ also delivers better delay fault coverage for high-speed I/O pads on the device. Hardware overhead is predictable and low. VirtualScan™ and UltraScan™ provide a smooth migration into existing scan ATPG flow and also provide diagnosis support.

TurboBIST™ - Built-in Self-Test
     view TurboBIST-Logic data sheet    view TurboBIST-Memory data sheet

TurboBIST™ family of products from SynTest includes built-in self-test tools for logic (TurboBIST™ - Logic) and memory (TurboBIST™ - Memory) (SRAM, ROM, DRAM and CAM). These tools provide synthesizable BIST logic for functional logic and memory blocks, including IP cores from third party suppliers, and automatically generate the test sessions needed to provide very high fault coverage testing of complete complex system-on-silicon chips.

TurboFault™ - Fault Simulation
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TurboFault™ family of tools combines high performance, versatility and accuracy. It is highly competitive with hardware accelerators for classical fault grading. It supports synchronous and asynchronous designs at the gate, behavior, and register-transfer levels, including tri-state gates, latches, flip-flops, single and multi-port RAMs, complex bus resolution functions, and User Defined Primitives (UDPs). TurboFault™ reads Verilog netlists, and Standard Delay Format (SDF) timing files.

TurboCheck™ - Testability Analysis
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TurboCheck™ is a Testability Analyzer and Test Assistant for both RTL (Register-Transfer-Level) and gate-level digital designs. TurboCheck™ analyzes the testability of sequential circuits and assists designers in selecting test solutions that are the most likely to improve the circuit's final fault coverage. TurboCheck operates on non-scan, partial-scan, or full-scan circuits. Because it is a static tool operating on the topology of the circuit, no vectors are needed for the analysis.

TurboScan - Scan Synthesis and ATPG      veiw data sheet

is an advanced full-scan DFT tool suite. It includes a Scan Synthesizer (optional) and an Automatic Test Pattern Generator (ATPG). TurboScan automatically repairs testability violations to make a design highly testable. The ATPG engine uses advanced search and compaction algorithms to achieve very high fault coverage and produce a very compact test pattern set. TurboScan™ is designed to reduce product defect level and save test costs.

TurboBSD™ - Boundary Scan
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TurboBSD™ is SynTest's high-performance Boundary-Scan Designer. It is fully compliant with the IEEE 1149.1 Boundary-Scan Standard. TurboBSD™ performs Boundary-Scan logic synthesis, creates BSDL (Boundary-Scan Description Language) file, and generates Boundary-Scan test patterns. All these tasks are fully automated by the tool, making Boundary-Scan design a straightforward process.

TurboDFT™ - Integration Tool Suite       view data sheet

TurboDFT™ is a useful and powerful DFT netlist integration and editing tool. TurboDFT™ allows users to automatically integrate, edit, and stitch DFT cores across circuit hierarchy, whether they are created using DFT tools from SynTest or other vendors. Easy-to-use effective scripts and commands are provided for allowing users to automatically stitch DFT cores with or without Boundary-Scan control. Thus, TurboDFT™ brings "Ease of integration" benefit and eliminates the tedious, error-prone manual hierarchical circuit stitching process.

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