RobustScan provides a platform for users to pick patented Configurable Soft-Error Resilience (CSER) cells or their preferred SER mitigation cells. First, Soft-Error Rate (SER) analysis is performed. Then it performs automatic robust-scan-cell and hardened-combinational-cell selection and synthesis. Finally it generates verification testbenches for the final design. RobustScan can be used with scan chains inserted using third-party tools; it can be linked to third-party's SER analysis programs and is fully compatible with SynTest's existing DFT tools for test, debug, and diagnosis.
DFT- PRO Plus - A Comprehensive Package of DFT Tools view data sheet
DFT-PRO Plus offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and Boundary-Scan Design (BSD) synthesis. The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow. This gives users the freedom to choose any commercially available logic and scan synthesis tools from vendors such as Cadence, Incentia, Mentor, or Synopsys and enables a one-pass RTL to GDSII synthesis flow. It also eases overall design floor planning.
TurboBIST family of products from SynTest includes built-in self-test tools for logic (TurboBIST - Logic) and memory (TurboBIST - Memory) (SRAM, ROM, DRAM and CAM). These tools provide synthesizable BIST logic for functional logic and memory blocks, including IP cores from third party suppliers, and automatically generate the test sessions needed to provide very high fault coverage testing of complete complex system-on-silicon chips.
TurboFault family of tools combines high performance, versatility and accuracy. It is highly competitive with hardware accelerators for classical fault grading. It supports synchronous and asynchronous designs at the gate, behavior, and register-transfer levels, including tri-state gates, latches, flip-flops, single and multi-port RAMs, complex bus resolution functions, and User Defined Primitives (UDPs). TurboFault reads Verilog netlists, and Standard Delay Format (SDF) timing files.
TurboCheck is a Testability Analyzer and Test Assistant for both RTL (Register-Transfer-Level) and gate-level digital designs. TurboCheck analyzes the testability of sequential circuits and assists designers in selecting test solutions that are the most likely to improve the circuit's final fault coverage. TurboCheck operates on non-scan, partial-scan, or full-scan circuits. Because it is a static tool operating on the topology of the circuit, no vectors are needed for the analysis.TurboScan - Scan Synthesis and ATPG veiw data sheet
TurboScan is an advanced full-scan DFT tool suite. It includes a Scan Synthesizer (optional) and an Automatic Test Pattern Generator (ATPG). TurboScan automatically repairs testability violations to make a design highly testable. The ATPG engine uses advanced search and compaction algorithms to achieve very high fault coverage and produce a very compact test pattern set. TurboScan is designed to reduce product defect level and save test costs.
TurboBSD - Boundary Scan view data sheet
TurboBSD is SynTest's high-performance Boundary-Scan Designer. It is fully compliant with the IEEE 1149.1 Boundary-Scan Standard. TurboBSD performs Boundary-Scan logic synthesis, creates BSDL (Boundary-Scan Description Language) file, and generates Boundary-Scan test patterns. All these tasks are fully automated by the tool, making Boundary-Scan design a straightforward process.
TurboDFT - Integration Tool Suite view data sheet
TurboDFT is a useful and powerful DFT netlist integration and editing tool. TurboDFT allows users to automatically integrate, edit, and stitch DFT cores across circuit hierarchy, whether they are created using DFT tools from SynTest or other vendors. Easy-to-use effective scripts and commands are provided for allowing users to automatically stitch DFT cores with or without Boundary-Scan control. Thus, TurboDFT brings "Ease of integration" benefit and eliminates the tedious, error-prone manual hierarchical circuit stitching process.
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