For Release October 19, 1998
Special
for editors attending ITC and EDA&T
For Information Contact: ITC booth
number 4
Georgia Marszalek, SynTest Public Relations Counsel, (650) 345-7477,
georgia@valleypr.com
SynTest Introduces a Fault Coverage Enhancer,
Enters the Windows NT Market, and Upgrades Its Testability Checker
and Fault Simulator
TurboFCE
improves fault coverage at the RT-level
NT version of TurboFCE and TurboCheck
available now, NT version of TurboFault available
Q1 ¡¯99 TurboFault and TurboCheck
upgrades available
Washington,
D.C.- October 19, 1998?International Test Conference --SynTest Technologies,
Inc.
(Sunnyvale, CA), an EDA company and supplier of Design-for-Test (DFT)
software tools for IC
designers and foundries, announced today that the company
is introducing TurboFCE ¢â,
a fault coverage enhancer for Verilog Register
Transfer-Level (RTL) designs, and expanding its
market beyond workstations
with Windows NT versions of TurboFCE, TurboCheck¢â,
an RTL and gate-level design
and test violation checker, and TurboFault¢â, a fast software fault
simulator.
And, the Company is offering upgrades to TurboCheck and TurboFault.
The new
products expand SynTest¡¯s market from UNIX to Windows NT, and extend SynTest's
product offerings for improving a design¡¯s testability and fault coverage.
L.-T.
Wang, SynTest Technologies¡¯ president, said, "Our goal is to provide a complete
DFT
solution to our customers. By adding Windows NT support, we are making
this solution available to
the growing number of designers who have selected
the PC as their platform."
New
Product TurboFCE for RTL Designs:
TurboFCE instruments the RTL code to
improve fault coverage. It does this by adding zero-delay
buffers to the RTL
representation so that a user can do fault grading at the RT-level.
TurboFCE
takes advantage of the correlation between a variable in the RTL design and wires
in the
synthesized gate-level circuit of the RTL design so that users can
inject faults at the inputs of the
buffers at RT-level. As a result, fault
grading at the RT-level produces fault coverage close to
a gate-level fault
grader, like SynTest¡¯s TurboFault fault simulator.
Wang,
noted, "100% code coverage does not guarantee the same level of fault coverage.
With TurboFCE, RTL fault coverage on the modified design is close to the fault
coverage for the
synthesized or gate-level representation of the design. And,
fault grading of RTL designs is much
faster than gate-level design fault grading."
TurboFCE works with popular RT-level fault simulators, such as Cadence¡¯s.
TurboFault
What¡¯s New:
TurboFault¡¯s speed has improved. According to one of SynTest¡¯s
customers, it runs up to 27
times faster than a hardware fault simulator --3
days vs. 82 days.
TurboFault adds a
comprehensive Tcl/Tk graphical user interface (GUI) operated on SUN Ultra Sparc.
It dumps a VCD output file so that a user can trace or debug any pattern mismatch
using a waveform
display like Design Acceleration¡¯s (DAI¡¯s). Toggle coverage
is also supported.
More About TurboFault:
TurboFault,
the fastest commercially available gate-level software fault simulator, helps
engineers
do a better and faster job of fault grading and managing the test
vectors used for manufacturing.
TurboCheck
What's New:
TurboCheck for RTL designs checks for design as well as test
rule violations, adds gate-level
checks to its RTL checks and verifies whether
the RTL design is synthesizable by popular
synthesis tools, such as those
from Synopsys and Ambit.
More About
TurboCheck:
TurboCheck identifies testability problems early in the design
cycle. Removing these problems
at the RTL stage reduces design iterations,
improves test insertion, Automatic Test Pattern
Generation (ATPG), and fault
coverage. TurboCheck checks RTL designs before synthesis
and verification.
Gate-level tests are used after synthesis.
TurboCheck
identifies most test rule violations, such as combinational feedback loops, generated
clocks, gated clocks, asynchronous set/reset, and floating busses. Its gate-level
checks pinpoint
the remaining test rule violations, including potential bus
contention and accessibility to embedded
RAMs and initialization of flip-flops
and latches. TurboCheck provides more thorough checking than
other solutions,
since it can separate generated clocks from gated clocks, and check whether
embedded
RAMs or flip-flops/latches are accessible or initializable from primary input
pins.
TurboCheck can be used as a front-end
tool to check for design errors. It checks if the design is
synchronous for
cycle-based RTL simulation and analysis, and structural-level design analysis
before and after logic synthesis.
TurboCheck
benchmarks show that for a typical design of 10,000 lines of Verilog RTL code,
it takes only a few minutes to identify and report the problems.
Pricing
and Availability:
TurboFCE is available now for UNIX workstations, including
Sun and Sun UltraSPARC and
the Windows NT platform. It starts at $10,000 (USD).
TurboCheck is available now for UNIX
workstations, including Sun and Sun UltraSPARC,
and the Windows NT platform.
TurboCheck starts at $20,000 (USD).
TurboFault
is available now for UNIX workstations, including Sun and Sun UltraSPARC.
The
Windows NT version ships in Q1, 1999. TurboFault starts at $50.000 (USD).
Customers with maintenance agreements receive TurboFault and TurboCheck upgrades.
About
SynTest:
SynTest Technologies, Inc. was founded in 1990 and is headquartered
in Sunnyvale, CA, USA
with offices in Japan, Taiwan and Korea. The company
develops and markets DFT software tools
and offers consulting services throughout
the world to semiconductor companies, ASIC designers
and test groups.
SynTest¡¯s
products include TurboFCE, a fault coverage enhancer; TurboBSD¢â, a boundary-scan
test suite; TurboCheck¢â, a gate-level and RTL-level design and testability analyzer;
TurboFault,
a fast fault simulator; and TurboScan¢â, a full-scan and partial-scan
synthesis and ATPG program.
SynTest Technologies,
Inc., 505 S. Pastoria Ave, Suite 101, Sunnyvale, CA 94086, USA,
408-720-9956,
Fax: 408-720-9960, info@SynTest.com,
http://www.syntest.com
###
Contacts
for Reader Inquiries:
SynTest Technologies, Inc., 505 S. Pastoria Ave,
Suite 101, Sunnyvale, CA 94086, USA
408-720-9956, Fax: 408-720-9960,
info@SynTest.com,
http://www.syntest.com
Attn: Elisabeth Calder
Notes
to editors:
Graphics available on request. Gary Smith, EDA analyst has
been briefed on these new products.
Contact Mr. Smith at 408-468-8271 or gsmith@dataquest.com
Acronyms
and definitions:
ASIC: Application Specific Integrated Circuit
ATPG:
Automatic Test Pattern Generation
DFT: Design-for-Test
EDA: Electronic Design
Automation
HDL: Hardware Description Language
IC: Integrated Circuit
RTL:
Register Transfer-Level (a design description above gate-level netlists)
Tcl/Tk:
Tool Command Language /Tool Kit used to build graphical user interfaces.
VCD:
Value Change Dump, a Verilog HDL format
Previous
Press Release: SynTest Adds Verilog RTL Capability to Its Testability Analyzer,
Chip Express Adds TurboCheck to Its ASIC Design Kits (January 26, 1998)
TurboFCE, TurboBSD, TurboCheck, TurboFault, and TurboScan are trademarks
of SynTest Technologies, Inc. All other trademarks are the property of their
respective owners.