Untitled Document

FOR IMMEDIATE RELEASE (January 26, 1998)
For Information Contact:
Georgia Marszalek, SynTest Public Relations Counsel
(650) 345-7477, georgia@valleypr.com

SynTest Adds Verilog RTL Capability to Its Testability Analyzer,
Chip Express Adds TurboCheck to Its ASIC Design Kits

Santa Clara, CA--January 26, 1998--DesignCon--SynTest Technologies, Inc. (Sunnyvale, CA),
a supplier and developer of test and verification solutions for integrated circuit designers and
foundries,announced that the company is adding a Register Tranfer-level (RTL) testability analyzer
-TurboCheck-RTL⑩ -to its product line. In addition, Chip Express (Santa Clara, CA), a fast-turn
ASIC supplier, announced that it has added TurboCheck to design kits for the company’s
LPGA (Laser Programmable Gate Array) product families.
TurboCheck-RTL complements and augments the company’s gate-level testability analyzer,
TurboCheck-Gate ⑩ (formerly called Pioneer). Another new product, TurboCheck⑩,
offers both gate and RTL test analysis.
TurboCheck-RTL identifies testability problems early in the design cycle. Removing these problems
at the RTL stage improves test insertion, Automatic Test Pattern Generation (ATPG), and fault
coverage. Using Turbocheck-Gate or TurboCheck-RTL helps reduce design iterations.
TurboCheck-RTL checks Verilog RTL designs before synthesis and verification. TurboCheck-Gate
is used after synthesis.
Ehud Yuhjtman, Vice-president of Engineering at Chip Express, noted, "We recognize
the importance of ASIC testability. We chose TurboCheck so our customers could further shorten
their design cycle by performing testability checks during an early design stage. With TurboCheck,
our customers can avoid surprises at the tail end of their design cycle, and can meet their design's
testability requirements. This coupled with our fast-turn ASIC capability helps them achieve
a time-to-market advantage."
According to L.-T. Wang, President of SynTest, "Checking the RTL version of a design for testability
rule violations, saves design iterations and helps designers achieve design-for-test goals sooner.
Up to 80% of the problems can be detected before synthesis with TurboCheck-RTL. After synthesis,
TurboCheck-Gate checks the gate-level design to further identify and zero-in on testability violations."
More About TurboCheck:
TurboCheck-RTL can identify most test rule violations, such as combinational feedback loops,
generated clocks, gated clocks, asynchronous set/reset, and floating busses. TurboCheck-Gat
e can further pinpoint remaining test rule violations, including potential bus contention and
accessibility to embedded RAMs and initialization of flip-flops and latches. TurboCheck provides
more thorough checking than other competing products, i.e., it can separate generated clocks
from gated clocks, and check whether embedded RAMs or flip-flops/latches are accessible or
initializable from primary input pins.
TurboCheck can also be used as a front-end tool to check if the design is synchronous for
cycle-based RTL and structural-level design analysis before and after logic synthesis.
TurboCheck-RTL Benchmark:
SynTest's TurboCheck-RTL benchmarks show that for a typical design of 10,000 lines of Verilog
RTL code, it takes only a few minutes to identify and report the problems.
About Chip Express and SynTest:
The companies have a joint development agreement. Chip Express uses SynTest’s TurboCheck
for test analysis and DFT checking, TurboScan⑩ for scan synthesis and ATPG, TurboFault⑩
for fault simulation and TurboBSD⑩ for boundary-scan design.
TurboCheck is part of Chip Express’ Design Kits. SynTest also provides test-related services to
Chip Express. SynTest tools?TurboCheck, TurboScan, TurboBSD, and TurboFault? are also
part of Chip Express’ standard design flow.
Chip Express’ Design Kits support ATPG without performance and density penalties.
This enables Chip Express customers to prepare their designs for test efficiently. Design Kits
with SynTest’s TurboCheck are available for the Chip Express QYH500, CX2000, CX2001
and CX2002 41k CMOS ASIC families.
Pricing and Availability:
TurboCheck runs on UNIX workstations, including Sun and Sun UltraSPARC. TurboCheck-Gate is
shipping now. A beta version of
TurboCheck-RTL is shipping now. Production versions ship in March.
TurboCheck-Gate is $10,000 (USD); TurboCheck-RTL is $20,000 (USD); TurboCheck with both
gate and RTL analysis is $25,000 (USD).
About Chip Express:
Chip Express is the world leader in the development and application of laser-based technology
for rapid customization of semiconductor devices.
The company’s unique capabilities allow personalization of gate arrays in a fast turnaround
as short as 1 day for prototyping, 1 week for low volume production and 1 month for volume
production.
Chip Express is a privately held corporation, founded in the US in 1989.
From its headquarters in Santa Clara, CA, Chip Express services leading-edge computer,
communications and military companies worldwide.
About SynTest:
SynTest Technologies, Inc. was founded in 1990 and is headquartered in Sunnyvale, CA, USA
with offices in Japan, Taiwan and Korea. The company develops and markets test and verification
tools and consulting services throughout the world to semiconductor companies, ASIC designers
and test groups.
SynTest Technologies, Inc., 505 S. Pastoria Ave, Suite 101, Sunnyvale, CA 94086, USA,
408-720-9956, Fax: 408-720-9960, info@SynTest.com, http://www.syntest.com
###
Contacts for Reader Inquiries:
SynTest Technologies, Inc., 505 S. Pastoria Ave, Suite 101, Sunnyvale, CA 94086, USA,
408-720-9956, Fax: 408-720-9960, info@SynTest.com, http://www.syntest.com
Attn: Elisabeth Calder
Chip Express, 2323 Owen Street, Santa Clara CA, 95054, USA
408- 988-2445, Fax: (408) 988-2449, info@chipx.com, http://www.chipexpress.com
Attn: Ms. Tsipi Landen
Note to editors:
TurboCheck data sheet and graphic of Chip Express’ design flow are available on request.
Acronyms:
ASIC: Application Specific Integrated Circuit
ATPG: Automatic Test Pattern Generation
DFT: Design-for-Test
IC: Integrated Circuit
RTL: Register Transfer-level (a design description above gate-level netlists)
Quotes:
Ehud Yuhjtman, (408) 235-7327, udi@chipx.com;
L.-T. Wang, (408) 720-9956, wang@syntest.com
Previous Press Release: Trident, Fujitsu, NEC and Silicon Motion Praise SynTest's Fault Simulator
(November 3, 1997)

TurboBSD, TurboCheck, TurboCheck-Gate, TurboCheck-RTL, TurboFault, and TurboScan are
trademarks of SynTest Technologies, Inc. All other trademarks are the property of their
respective owners.