FOR RELEASE NOVEMBER 3, 1997 ITC Booth 2701
For Information Contact:
Georgia Marszalek, SynTest, Public Relations Counsel
(650) 345-7477 FAX: (650) 341-0388, firstname.lastname@example.org
Trident, Fujitsu, NEC, and Silicon Motion Praise SynTest's Fault Simulator
TurboFault Adds Distributed Fault Simulation, SDF Support, DAI Interface
Washington DC--November 3, 1997 - International Test Conference (ITC)-
-SynTest Technologies, Inc., a supplier and developer of test and verification solutions for integrated
circuit (IC) designers and foundries, announced today that Fujitsu, NEC, Trident, and Silicon
Motion report that TurboFault is faster than other solutions.
In addition, SynTest is announcing major upgrades to TurboFault-Version 2.1 and Version 2.2.
TurboFault, the fastest commercially available software fault simulator, helps engineers do a better
and faster job of fault grading and managing the test vectors used for manufacturing.
L.-T. Wang, President and Founder of SynTest, said, "TurboFault is one of our most successful
products. In Version 2.1, we added features like load balancing for distributed fault simulation
to answer customers' requests for even faster fault simulation."
According to Benson Cheung, SynTest's Director of Business Development and Consulting
Engineering, "To further speed up the fault grading process, distributed fault simulation technology
in TurboFault automatically partitions a designĄ¯s fault list, dividing the fault simulation tasks
among several processors."
Version 2.2 of TurboFault adds Standard Delay Format (SDF) support to improve accuracy
for timing dependent modules, and an interface to Design Acceleration's (San Jose, CA) DAI
SignalScan DX waveform viewer and schematic generation tool to enhance the simulation analysis
and debugging environment. Cheung noted, "The interface to SignalScan shortens the time
to debug logic simulation mismatches, allowing users to start fault grading much earlier. We also
added support to DAIĄ¯s SST2 database format. This format has built-in compression technology
to compress test vector data 10 to 100 times more than VerilogĄ¯s VCD format to conserve
disk space. "
What Customers Say:
Minoru Takeno, Telecom Design Manager of Fujitsu (Japan), stated, "We ran benchmarks
on designs of 100,000 to 250,000 gates and found TurboFault to be six to 15 times faster than
two other commercial fault simulators."
According to Masaaki Yoshida, Engineering Manager, NEC (Japan), "We did six benchmarks
using TurboFault. Our results were two to 12 times faster than another solution."
Jens Olson, Senior Design Engineer of Trident Microsystems (Mountain View, CA), a manufacturer
of graphics acceleration systems for notebook, desktop and multimedia PC applications, said,
"We tested TurboFault on a 500,000 gate ASIC with over 20 different memory models. The results
matched our Verilog simulation. TurboFault ran 3.5 times faster than a competing tool that we
evaluated. By using TurboFault, we reduced our run time by days."
Mark Wong, Director of Technology and Manufacturing at Silicon Motion (San Jose, CA), a graphics
chip manufacturer, added, "We benchmarked TurboFault on a 150,000 gate design with many
memory models. By using TurboFault, we were able to increase our fault coverage of our design
from 60% to 90% in just three months."
Pricing and Availability:
TurboFault runs on SUN SPARC workstations, including Sun OS and Solaris, and HP 700 series
workstations. Version 2.1 with distributed fault simulation in shipping now. Version 2.2 with SDF
support and the DAI interface ships in December. The price starts at $50,000 (USD).
SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA
94086, USA, 408-720-9956, Fax: 408-720-9960, email@example.com, Attn.: Elisabeth Calder
SynTest Technologies, Inc. was founded in 1990 and is headquartered in Sunnyvale, CA, USA
with offices in Taiwan, Japan and Korea. The company develops and markets test and verification
tools and consulting services throughout the world to semiconductor companies, ASIC designers
and test groups.
Contact for Reader Inquiries:
SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, Sunnyvale, CA 94086, USA,
408-720-9956, Fax: 408-720-9960,
http://www.syntest.com, info@SynTest.com, Attn: Elisabeth Calder
ASIC: Application Specific Integrated Circuit
ATPG: Automatic Test Pattern Generator
DAI: Design Acceleration, Inc.
HDL: Hardware Description Language
IC: Integrated Circuit
SDF: Standard Delay Format
VCD: Value Change Dump
Data sheets, electronic versions of graphics or screen shots are available on request.
Previous Press Release: SynTest Introduces New Version of Its ATPG Tool (June 9, 1997)
TurboFault is a trademark of SynTest Technologies, Inc. All other trademarks are the property of
their respective owners.