FOR IMMEDIATE RELEASE
For Information Contact:

Georgia Marszalek, SynTest, Public Relations Counsel
(415) 345-7477, FAX: (415) 341-0388, georgia@valleypr.com

 

SYNTEST TECHNOLOGIES INTRODUCES FAST FAULT SIMULATOR

TurboFault Targets ASIC Design and Test Teams,
Offers Fast Simulation and Improves Memory Utilization

Sunnyvale, CA--December 30, 1996--SynTest Technologies, Inc., a supplier and developer of test
and verification solutions for integrated circuit (IC) designers and foundries, is introducing
TurboFault(TM), the fastest fault simulator commercially available for ASIC design and test teams
who need to improve and speed-up their fault grading processes.

TurboFault is the fastest commercially available fault simulator available. It helps engineers do
a better job grading and managing the test vectors used for manufacturing. TurboFault is a software
solution that is two to 100 times faster than competitive products, including hardware accelerators
used for fault simulation. TurboFault costs five times less than hardware accelerators. In addition,
TurboFault improves memory utilization.

According to L. T. Wang, SynTest's founder and president, "Our focus is test and verification.
Our customers are semiconductor companies and ASIC designers, who use our automated test
solutions and consulting services to reduce expensive tester time, and improve quality and
time-to-market.

"Before developing TurboFault, we surveyed the market to see how our fault simulation solution
could make a difference. Customers asked us to improve simulation turnaround time and memory
utilization. We developed new technologies to do this. Our Cached-Concurrent (TM) technology
reduces the number of gate-evaluations, and our Fast Queue (TM) technology combines the best
of cycle-based and event-driven simulation to improve performance."

Test Grading--Proven Results:

Recently, a SynTest customer used TurboFault to grade faults for a 100,000 gate ASIC with
154,000 faults and 60,000 vectors. On an UltraSPARC 170, this took 1.5 hours and resulted in
60% fault coverage. The closest competitive product evaluated took four hours. According to
Robert Dahlberg, Syntest's director of marketing, "As a result of our new technology, our beta
customers are using up to 50% less memory for the same or similar designs because of our
new algorithms."

More about TurboFault:

TurboFault supports industry standards such as IEEE 1076 (VHDL) and IEEE 1364 (Verilog HDL),
and EDIF 2.0.0. TurboFault uses new algorithms to improve performance --the Cached- Concurrent
(TM) algorithm eliminates needless evaluations; the Fast Queue(TM) algorithm combines the best
features of cycle-based and event-driven simulation to improve performance. TurboFault supports
single timing delay for simulation accuracy. It handles synchronous and asynchronous designs
at the gate level, including tri- state gates, latches, flip-flops, single and multi-port RAMs, complex
bus resolution functions, and User-defined primitives (UDPs). TurboFault accepts as input:
Verilog VCD, WGL, TDL gate-level netlists, Standard Delay Format (SDF) timing files, and patterns
from Syntest's ATPG solutions, Pioneer and Picasso. It generates reports on fault coverage and
classification. Pioneer and Picasso can directly access undetected faults for improving fault
coverage.

Pricing and availability:

TurboFault runs on UNIX workstations, including Sun and Sun UltraSPARC. Shipments begin
next month. The price starts at $50,000 (USD).

SynTest products:

Syntest's other products include: its testability analysis tool-Pioneer; full scan, partial scan and
sequential ATPG-Picasso; scan synthesis and RAM BIST tool-Pyramid; boundary scan test
tool-Protocol.

For information contact:
SynTest Technologies, Inc., 505 S. Pastoria Ave, Suite 101, Sunnyvale, CA 94086, USA,
408-720-9956, Fax: 408-720-9960, info@syntest.com. SynTest Technologies, Inc.
was founded in 1990 and is headquartered in Sunnyvale, CA, USA with offices in Taiwan and
Japan. The Company develops and markets test and verification tools and consulting services
throughout the world to semiconductor companies and ASIC designers. SynTest has over 40
customers worldwide. Customers include: Alliance Semiconductor, Chip Express, Cirrus Logic,
Cisco, 8X8, Fujitsu, RISE, Oki Semiconductor, Motorola, Orbit Semiconductor, Sony, Trimble
Navigation, TSMC and UMC.

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Acronyms:

ASIC: Application Specific Integrated Circuit
ATPG: Automatic Test Pattern Generator
BIST: Built-in-Self-Test
HDL Hardware Description Language
IC: Integrated Circuit
RAM: Random Access Memory
ROI: Return-on-Investment
SDF: Standard Delay Format
TDL : Test Data Language
VCD: Verilog Change Dump (file)
WGL : Waveform Generation Language

Note to editors: Data sheets, electronic versions of .graphics or screens are available on request.

Enclosure: TurboFault Data Sheet TurboFault, Cached-Concurrent, and Fast Queue are trademarks
of SynTest Technologies, Inc. All other trademarks are the property of their respective owners.

 



Specifications subject to change without notice.

Verilog is a trademark of Cadence Design System, Inc.All trademarks and registered trademarks
are the property of their respective companies.