SPECIAL FOR EDITORS ATTENDING ITC 1996
SynTest Technologies Booth Number 2909

FOR IMMEDIATE RELEASE

Contact: Georgia Marszalek, SynTest, Public Relations Counsel
(415) 345-7477, FAX: (415) 341-0388, georgia@valleypr.com

 

SYNTEST TECHNOLOGIES DEMONSTRATES ITS TEST

AND VERIFICATION PRODUCTS

 

AT 1996 INTERNATIONAL TEST CONFERENCE

Demonstrations and Benchmarks Show How SynTest's Test and
Verification Products Reduce Tester Time by 20-50% and Improve Time-To-Market

Washington DC--October 22, 1996--International Test Conference---SynTest Technologies, Inc.
(Sunnyvale, CA, USA), a supplier and developer of test and verification solutions for integrated
circuit (IC) designers and foundries, will be demonstrating its test and verification products
(Picasso, Pioneer, Pyramid, Protocol) and previewing a new fault simulator at the 1996 International
Test Conference, October 22-24, at their Booth #2909.

The company's demonstrations feature its testability analysis tool-Pioneer; full scan, partial scan
and sequential ATPG-Picasso; scan synthesis and RAM BIST tool-Pyramid; boundary scan test
tool-Protocol; and a new product, TurboFault(TM). TurboFault is a fault simulator that will be
announced to the press later this year.

According to L. T. Wang, SynTest founder and president, "SynTest's focus is test and verification.
We supply semiconductor companies and IC designers with test solutions and consulting services.
At this year's ITC we are demonstrating our products and offering ITC attendees benchmark and
ROI information that shows how our products reduce tester time and improve time- to-market."

Robert Dahlberg, SynTest's Director of Marketing, noted, "Our customers report results that prove
our ATPG vector compaction technology saves them 20 to 50% of their tester time, and our fault
simulator customers have run benchmarks showing that TurboFault is faster than hardware
acceleration."

Pricing and availability:

Pioneer, Picasso, Pyramid and Protocol are shipping now. Product prices start at $10,000(US).
A complete tool package is $165,000(US). SynTest products run on UNIX workstations,
including Sun and Sun UltraSPARC. TurboFault will be announced later this year.

For information contact:

SynTest Technologies, Inc., 505 S. Pastoria Ave, Suite 101, Sunnyvale, CA 94086, USA,
408-720-9956, Fax: 408-720-9960, info@syntest.com.

SynTest Technologies, Inc. was founded in 1990 and is headquartered in Sunnyvale, CA, USA
with offices in Taiwan and Japan. The Company develops and markets test and verification tools
and consulting services throughout the world to semiconductor companies and IC designers.

SynTest has over 40 customers worldwide. Customers include: Alliance Semiconductor,
Chip Express, Cirrus Logic, Cisco, 8X8, Fujitsu, RISE, Oki Semiconductor, Matra MHS,
Orbit Semiconductor, Samsung, Sony, Trimble Navigation, TSMC and UMC.

###

Acronyms:

ASIC: Application Specific Integrated Circuit
ATPG: Automatic Test Pattern Generator
BIST: Built-in-Self-Test
IC: Integrated Circuit RAM: Random Access Memory
ROI: Return-on-Investment
Note to editors: Graphics or electronic screen files available on request.
TurboFault is a trademark of SynTest Technologies, Inc.

All other trademarks are the property of their respective owners.

Syntest at ITC Page of 2


Specifications subject to change without notice.

Verilog is a trademark of Cadence Design System, Inc.

 

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