TSMC and SynTest


TSMC (Taiwan Semiconductor Manufacturing Company, Ltd.) and SynTest Technologies announce
their partnership for test pattern generation and test logic synthesis services to TSMC ASIC
customers.San Jose, Calif., April 12, 1995 -- TSMC (Hsinchu, Taiwan) and SynTest Technologies
(Sunnyvale, CA and Hsinchu, Taiwan) jointly announced today their plans to partner to provide
ASIC customers of TSMC with industry-leading services for enchancing testability and fault coverage
of complex circuit designs. These services include: Testability analysis, test logic synthesis and
automatic test pattern generation (ATPG) for full-scan and partial-scan designs Testability analysis
and automatic test pattern generation for non-scan designs Boundary-scan logic synthesis,
IEEE 1149.1 conformance or verification test pattern generation, and BSDL file generation
Built-in Self-Test (BIST) logic synthesis for RAMs and random logic blocks Fault simulation and
full-scan/bonudary-scan fault diagnosis Scan/simulation pattern conversion.



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