Elsevier New Textbook serves as Comprehensive Guide for Latest,
Up-to-Date Technologies of Design-for-Testability

"VLSI Test Principles and Architectures: Design for Testability"

SAN JOSE, Calif., July 19, 2006 -- SynTest Technologies, Inc., a leading supplier of Design-for-Test (DFT) tools, announced the availability on July 7, 2006 of "VLSI Test Principles and Architectures: Design for Testability" a most recent textbook co-edited by SynTest founder and CEO, Dr. Laung-Terng Wang, and published by Morgan Kaufmann Publishers, an Elsevier company. The other two co-editors are Prof. Cheng-Wen Wu of National Tsing Hua University, Taiwan, and Prof. Xiaoqing Wen of Kyushu Institute of Technology, Japan.

With introduction of new nanometer technologies that use 90 nanometers or smaller geometry, semiconductor test costs have been growing steadily and it is important to attack this cost increase as well as tackle new problems associated with nanometer devices. This has led to a renewed interest in DFT methodologies and technologies. This new book is a comprehensive guide to new as well as existing, well-proven DFT techniques that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, as well as speed up time-to-market and time-to-volume.

"Most importantly, the book covers industry practices commonly found in commercial DFT tools but not discussed in other books", said Dr. Ravi Apte, Vice President of Strategy and Business Development at SynTest Technologies, Inc., "There are many recent advances covered in the book, including at-speed testing for scan and logic built-in self-test (BIST) applications, test compression for reducing scan test cost, memory fault simulation, DRAM BIST, memory built-in self-repair (BISR), and future test technology trends. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures make this book a very valuable reference for engineers and managers practicing in the DFT field."

For more information and many other valuable quotes from DFT veterans, please refer to the Elsevier website: http://www.elsevier.com/inca/707926.

Priced at $59.95, the 808-page book is now available for shipment. A book signing event, sponsored by DAC and intended for authors of new, 2006 books will be held on Monday afternoon between 4:15PM and 5:15PM, on booth 2228.

About SynTest
SynTest Technologies, Inc., established in 1990, develops intellectual properties (IPs) for advanced design-for-test (DFT) and design-for-debug/diagnosis (DFD) applications and markets them throughout the world, to semiconductor companies, system houses and design service providers. The company has filed more than 25 US/PCT patents of which 5 have been issued and 2 allowed. The Company's products improve an electronic design's quality and reduce overall design and test costs. Various applications that use these IPs include logic BIST, memory BIST, boundary-scan synthesis, scan/ATPG with test compression, concurrent fault simulation, silicon debug and diagnosis. The company headquartered in Sunnyvale, California, has offices in Taiwan, Japan, Korea and China, and distributors in Europe and Asia including Israel. More information is available at www.syntest.com.

SynTest Technologies Inc. is headquartered at 505 South Pastoria Ave., Suite 101, Sunnyvale, California 94086, Phone: 408-720-9956, E-Mail: info@syntest.com

SynTest and TurboBIST-Logic are trademarks of SynTest Technologies, Inc. All other trademarks are property of their respective owners.

For more information:
SynTest contact info: Ravi Apte
Tel:1- 408-720-9956 ext. 300