SynTest Receives A Fundamental Patent for At-Speed Capture Invention for Logic BIST

"Multiple-capture DFT system for Detecting or Locating
Crossing Clock-domain faults during Self-test or Scan-test"

SAN JOSE, Calif., Feb 28, 2006 -- SynTest Technologies, Inc., a leading supplier of Design-for-Test (DFT) tools, was granted 30 claims on Feb. 28, 2006 under United States patent number 7,007,213 for its invention of At-Speed capture for detection of faults using Logic BIST DFT scheme for multiple clock domain designs.

Dr. L-T. Wang, founder, president, CEO of SynTest states, ¡°This patent applies directly to our innovative Logic BIST product offering being used by many leading corporations in the world. It is one of the most critical patents ever granted by the US Patent Office. This patented approach allows us to help our customers improve quality of the devices they produce today in sub-micron technologies containing multi-clock domains running at very high frequencies by self-testing each clock domain At-Speed."

The patented invention are methods and apparatus for providing ordered capture clocks, each running at its intended speed, to detect or locate faults within each clock domain and faults across clock domains in an integrated circuit in self-test mode, where each domain has scan chains. Dubbed ¡°staggered launch-on-capture¡± or ¡°staggered double-capture¡±, the capture-clocking scheme allows designs containing synchronous and asynchronous clock domains to perform self-test at-speed. SynTest TurboBIST-Logic product is based on this technology invention. A slow Scan-Enable control signal, as commonly used for slow-speed or at-speed scan testing, in the patented invention also eliminates hard-to-implement timing constraints imposed by other competing synchronous, clock-sub-multiple schemes that are implemented by competing products, resulting in improved productivity and time-to-market (TTM).

About SynTest

SynTest Technologies, Inc., established in 1990, develops IP for advanced design-for-test (DFT) and design-for-debug/diagnosis (DFD) applications and markets them throughout the world, to semiconductor companies, system houses and design service providers. The company has filed more than 20 US/PCT patents of which 3 have been issued and 2 allowed. The Company¡¯s products improve an electronic design¡¯s quality and reduce overall design and test costs. Various applications that use these IP (intellectual properties) include logic BIST, memory BIST, boundary-scan synthesis, Scan/ATPG with test compression, concurrent fault simulation, silicon debug and diagnosis. The company headquartered in Sunnyvale, California, has offices in Taiwan, Japan, Korea and China, and distributors in Europe and Asia including Israel. More information is available at www.syntest.com.

SynTest Technologies Inc. is headquartered at 505 South Pastoria Ave., Suite 101, Sunnyvale, California 94086, Phone: 408-720-9956, E-Mail: info@syntest.com

SynTest and TurboBIST-Logic are trademarks of SynTest Technologies, Inc. All other trademarks are property of their respective owners.

Acronyms:
ATPG: Automatic Test Program Generation
BIST: Built-In Self-Test
DFT: Design-for-Test
DFD: Design-for-Debug/Diagnosis
IP: Intellectual Property
TTM: Time-to-Market

For more information:
SynTest contact info: Ravi Apte
Tel:1- 408-720-9956 ext. 300