Acronyms:
SynTest Receives "Computer-aided design system to automate scan synthesis
at register-transfer level" Patent for RTL Scan Synthesis Invention
Elevating Scan Synthesis to RTL helps improve design
quality and reduce design time
SAN JOSE, Calif., Oct 25,
2005 -- SynTest Technologies, Inc., a leading supplier of Design-for-Test
(DFT) tools, was granted 68 claims on Oct. 18, 2005 under United States
Patent # 6,957,403 for its invention of inserting scan structures
in RTL (register-transfer level) description of synchronous and asynchronous
multi-clock, multi-frequency designs.
The patented invention makes a profound impact on the current design implementation
methodology and flow from RLT to GDS II. By moving scan synthesis to RTL,
it helps improve design quality and reduce development time. Scan synthesis
in asynchronous multi-clock, multi-frequency design forces most of the
current flows to deal with gate-level of abstraction. The patent method
provides interactive scan debug, interactive scan repair, and flash/random
test bench generation at the RTL. In addition, it facilitates hierarchical
scan synthesis by performing scan synthesis module-by-module and then
stitching these scanned module together at the top-level.
Furthermore, this patented scan synthesis scheme (1) performs RTL testability
analysis and RTL scan selection/repair/stitching, (2) reduces the number
of clocks and ATPG patterns by allowing scan flip-flops in non-interacting
clock domains to perform scan testing simultaneously, and (3) facilitates
test point selection and insertion at the RTL for ease of future test
point ECO at the gate-level.
About SynTest:
SynTest Technologies, Inc., established in 1990, develops IPs for advanced
design-for-test (DFT) and design-for-debug/diagnosis (DFD) applications
and markets them throughout the world, to semiconductor companies, system
houses and design service providers. The company has filed more than 20
US patents. The Company¡¯s products improve an electronic design¡¯s quality
and reduce overall design and test costs. Various applications that use
these IPs include logic BIST, memory BIST, boundary-scan synthesis, Scan/ATPG
with test compression, concurrent fault simulation, silicon debug and
diagnosis. The company headquartered in Sunnyvale, California, has offices
in China, Taiwan, Korea and Japan, and distributors in Europe and Asia
including Israel. More information is available at www.syntest.com.
SynTest Technologies Inc. is headquartered at 505 South Pastoria Ave.,
Suite 101, Sunnyvale, California 94086, Phone: 408-720-9956, E-Mail:
info@syntest.com
SynTest is a trademark of SynTest Technologies, Inc. All other trademarks
are property of their respective owners.
ATE: Automatic Test Equipment
ATPG: Automatic Test Program Generation
BIST: Built-In Self Test
BSD: Boundary Scan Design
DFD: Design for Debug/Diagnosis
DFT: Design For Test
For more information:
SynTest contact info:
Nayan Pradhan, Senior Marketing Manager,
Tel:1- 408-720-9956 ext. 301, nayan@syntest.com