At D.A.T.E., SynTest to Showcase Integrated RTL-to-GDSII DFT Flow Featuring
Integrated flow simplifies test implementation and
improves overall design turnaround time
SUNNYVALE, Calif., February 16, 2004 - SynTest Technologies, Inc., a leading
supplier of Design-for-Test (DFT) tools, today announced that it would
be showcasing an integrated RTL-to-GDSII DFT flow at the Design Automation
and Test in Europe (DATE) Exhibition, February 17-19 in Paris. The flow
- featuring the Magmaç (Nasdaq: LAVA) Blast Createâ and Blast
Fusionç software, and the SynTest DFT-PRO Plusâ software
- was developed by SynTest through the MagmaTies partner program. In initial
testing, Magma's software was shown to reduce ASIC design time, and cost
and SynTest's software was shown to improve the design's testability while
reducing test cost.
The integrated Magma/SynTest flow provides a comprehensive design environment
that includes DFT, allowing designers to focus on critical design issues
rather than tool integration issues. Adding the DFT structures to the
RTL enables designers to quickly carry out "what-if" analysis, and makes
the impact of the DFT structures on area, timing, power much more predictable.
Further, checking and fixing of testability rules violations at the RT
level helps avoid expensive iterations. This is typically required in
traditional flows where the checking is done at the gate-level, after
synthesis in the design process.
"With rapidly growing SoC design complexity and size, inserting DFT schemes
at the netlist level of abstraction is proving to be a hindrance due to
its effect on timing, chip layout planning and implementation. Hence,
SynTest DFT-PRO Plus has moved total DFT insertion and DFT rules violation
checking & fixing to the RT level. This enables SynTest and Magma,
with its Blast Create and Blast Fusion, to offer an integrated RTL-to-GDSII
DFT flow that significantly cuts down design costs and time," said Dr.
Ravi Apte, senior vice president of strategic marketing for SynTest. "With
this integration, our VirtualScan with XtremeCompactâ test data
vectors significantly reduces test costs by using a large number of short
scan chains and is easier to synthesize into the design because floor
planning, timing and power are taken care of upfront."
"A comprehensive DFT feature set is required for all complex designs.
SynTest's DFT solution integrates conventional and advanced DFT features
in RTL form, providing improved testability for SoC designs without compromising
the benefits of an integrated flow, leading to better quality of results
and ease of timing closure," said Yatin Trivedi, director of product marketing
at Magma Design Automation. "Through interoperability work with SynTest,
Magma ensures that customers have flexibility and choice in their DFT
DFT-PRO Plus offers an integrated DFT solution covering virtual
scan synthesis and ATPG, memory BIST, and boundary-scan (JTAG) technologies.
The corresponding tools generate RTL blocks that fit seamlessly into an
existing synthesis flow and enable a one-pass RTL to GDSII synthesis flow,
which eases overall design floor planning. VirtualScan helps get a 5x
to 50x reduction in the cost of semiconductor testing.
Also included in the package are tools for checking DFT violations and
integrating various DFT blocks and design RTL codes. The DFT rules checker
can, as an option, offer automatic DFT repair by generating repair logic
at RTL, which can alleviate the tedious manual coding at RTL to repair
the DFT check violations.
SynTest Technologies, Inc., established 1990, develops and markets advanced
design-for-test (DFT) and design-for-debug/diagnosis (DFD) tools throughout
the world, to semiconductor companies, system houses, and design service
providers. The company's products improve an electronic design's testability
and fault coverage and result in reduced defect levels and reduced slippage
in time-to-market (TTM). The products also reduce overall design and test
costs, by helping to reduce design iterations as well as the time and
reloads on automatic test equipment (ATE). These products include tools
for logic BIST, memory BIST, boundary-scan synthesis, DFT testability
analysis, VirtualScan synthesis and ATPG with XtremeCompact test vectors,
concurrent fault simulation, silicon debug and diagnosis. The company,
headquartered in Sunnyvale, California, has offices in Taiwan, Korea Japan
and China, and distributors in Europe and Asia including Israel. More
information is available at www.syntest.com.
Information about Magma's Blast Create, Blast Fusion and other products
can be found at http://www.magma-da.com.
SynTest, DFT-PRO Plus,
VirtualScan, and XtremeCompact are trademarks of SynTest Technologies,
Inc. Magma and Blast Fusion are registered trademarks and Blast Create
is a trademark of Magma Design Automation. All other trademarks are property
of their respective owners.
Except for the historical information contained herein, the matters set
forth in this press release, including statements that the SynTest/ Magma
DFT flow reduces design and test time and cost and statements about the
features and benefits of Magma¯s and SynTest's software are forward-looking
statements within the meaning of the "safe harbor" provisions
of the Private Securities Litigation Reform Act of 1995. These forward-looking
statements are subject to risks and uncertainties that could cause actual
results to differ materially including, but not limited to the ability
of Magma's products to produce the desired results and Magma's ability
to keep pace with rapidly changing technology. Further discussion of these
and other potential risk factors may be found in the parties¯ latest
filings with the Securities and Exchange Commission on form 10-K, and
any subsequent updates thereto on form 10-Q. These forward-looking statements
speak only as of the date hereof. The parties disclaim any obligation
to update these forward-looking statements.
ASIC: Application Specific Integrated Circuits
FPGA Field Programmable Gate Arrays
ATE: Automatic Test Equipment
IC: Integrated Circuits
ATPG: Automatic Test Program Generation
IDM: Integrated Device Manufacturer
BIST: Built-In Self-Test IP Intellectual Property
MNC: Multi-National Company
EDA: Electronic Design Automation
For more information:
SynTest contact info: Nayan Pradhan, Senior Marketing Manager,
Tel:1- 408-720-9956 ext. 301, firstname.lastname@example.org