Teseda Validation Systems Plus SynTest Diagnosis Software Shorten
Time For Diagnosing DFT-Based Designs

Portland, Ore. and Sunnyvale, Calif.,- August 18, 2003 - Portland-based Teseda Corporation, a leader in design-for-test (DFT) validation systems, and Sunnyvale-based SynTest Technologies, a leading provider of DFT technology, announced today that they are teaming to deliver fast, accurate failure diagnostics for deep-submicron, system-on-chip (SoC) designs. The two companies have partnered to streamline and facilitate communications between Teseda's V500™. and SynTest's new ATE-based debug and failure analysis software, TurboDiagnosis., for optimized discovery of device failures. The flow provides increased productivity and quality, as well as reduced cost to engineers who need to validate, debug, characterize, analyze, or sample integrated circuits (ICs) based on DFT.

The DFT Test Link

Teseda's V500 is a laptop-sized, affordable test system that design and product engineers use to accelerate DFT-based engineering test processes, such as chip and test validation and debug, fault isolation, and sample qualification.

The V500 system receives ATPG and testbench data from SynTest's DFT tools via an integrated, bi-directional communication link, then transfers the failure data to SynTest's debug and failure analysis software, TurboDiagnosis. TurboDiagnosis analyzes the data and automatically generates diagnostic patterns to precisely identify the failing node and discover the most likely causes of the defect.

TurboScan is SynTest's time-proven scan insertion and compact ATPG tool. VirtualScan provides scan insertion and compressed ATPG with VirtualScan capability to generate XtremeCompact™ scan test patterns. This reduces the cost of semiconductor testing by a factor of 5x to 50x through reduced test data volume, test run time, and test system reloads.
Together, the SynTest DFT and design-for-debug/diagnosis (DFD) tools, and the V500 create a fully integrated flow that minimizes the time-to-production for DFT-enabled devices. The integrated flow is based on the IEEE standard 1450 Standard Test Interface Language (STIL). The flow supports direct transfer of ATPG patterns from SynTest's TurboScan™ or VirtualScan™ to the V500 for engineering test.

"With SynTest's state-of-the-art DFT capabilities and our own expertise in DFT test, together we can now help mutual customers' engineers achieve faster time-to-volume with better test quality for their complex SoC designs" said Steve Morris, president and CEO, Teseda Corporation. "We are making it easier for engineers to have a cost-effective, smooth, and productive DFT flow with the integration to SynTest's platforms. Furthermore, this partnership lets SoC manufacturers realize dramatic cost savings over using traditional ATE as a tool for DFT-based engineering test."

"SoC markets today require shorter turnaround times to bridge the technical gap between design and production-test teams." According to Dr. L.T. Wang, president and chief executive officer, SynTest Technologies, "Providing customers with an automated diagnostic flow reduces the amount of time required for prototype debug and failure analysis and, more importantly, accelerates yield improvements and volume production of advanced SoC devices. This partnership with Teseda helps reduce the barrier between design and prototype test by linking best-in-class products in an intuitive and transparent flow."

ITC Attendees Can View Industry-First Demonstration
The complete design-to-test-to-diagnosis Teseda-SynTest flow will be demonstrated at the International Test Conference, in Charlotte, NC, Sept. 30 to Oct. 2, 2003 at the Teseda (#1029) and SynTest (# 1024) booths. Stop by or make an appointment for a demonstration.

About Teseda Corporation
Teseda Corporation of Portland, Oregon, is founded on the overriding idea that adoption of design-for-test is resulting in a disruptive change in the IC test industry that will change the way integrated circuits are tested. Teseda's mission is to provide DFT-Focused test solutions that dramatically reduce test cost and accelerate time-to volume.
For more information, visit www.teseda.com.

About SynTest
SynTest Technologies, Inc., est. 1990, develops and markets advanced design-for-test (DFT) and design-for-debug/diagnosis (DFD) tools throughout the world, to semiconductor companies, system houses, and design service providers. The company's products improve an electronic design's testability and fault coverage and result in reduced defect levels and reduced slippage in time-to-market (TTM). The products also reduce overall design and test
costs, by helping to reduce design iterations as well as the time and reloads on automatic test equipment (ATE). These products include tools for logic BIST, memory BIST, boundary-scan synthesis, DFT testability analysis, VirtualScan synthesis and ATPG with XtremeCompact. test vectors, concurrent fault simulation, silicon debug and diagnosis. The company, headquartered in Sunnyvale, California, has offices in Taiwan, Korea and Japan, and distributors in Europe and Asia including Israel. More information is available at www.syntest.com.

Teseda, the Teseda logo, Validator 500, V500, and DFT-Focused are trademarks of Teseda Corporation. SynTest, TurboScan, VirtualScan, XtremeCompact and TurboDiagnosis are trademarks of SynTest Technologies, Inc. All other trademarks are property of their respective owners.

ASIC: Application Specific Integrated Circuits
ATE: Automatic Test Equipment
ATPG: Automatic Test Program Generation
BIST: Built-In Self-Test
DFT: Design-for-Test
DFD: Design-for-Debug/Diagnosis
IDM: Integrated Device Manufacturer
RTL: Register Transfer Level
SoC: System-on-Chip

For more information:
Andrew Levy, Director of Marketing Teseda Corporation,
503-223-3315 ext. 204, andrew_levy@teseda.com

Hadewych Verlinden, Public Relations for Teseda, Armstrong Kendall, Inc.
503-672-4684, hadewych@akipr.com

Nayan Pradhan, Senior Marketing Manager, SynTest Technologies, Inc.
408-720-9956 ext. 301, nayan@syntest.com