SynTest Announces DFT-PRO Plus
Comprehensive package of DFT tools for One-Pass RTL DFT synthesis
with VirtualScan ATPG
SUNNYVALE, California, June 2, 2003 . Design-for-Test (DFT) leader
SynTest Technologies today announced release of DFT-PRO Plus,
a comprehensive software package of Design-for-Test (DFT) tools for One-Pass
RTL DFT synthesis with VirtualScan ATPG to improve an ASIC design's testability
and fault coverage, at an affordable cost.
All DFT insertion using DFT-PRO Plus is handled at the Register
Transfer Level (RTL), thereby moving DFT insertion ahead of logic synthesis
in the flow. The DFT tools generate RTL blocks that can be easily synthesized
and incorporated into the design flow using any commercially available
logic and scan synthesis tools from vendors like Cadence, Get2Chip, Incentia,
Magma, Mentor, Synopsys or Synplicity. As the DFT blocks are at RTL, this
also eases the overall design floor planning decisions carried out at
the RTL stage.
DFT-PRO Plus includes a complete set of well-integrated
tools for DFT implementation schemes, including scan synthesis and ATPG,
boundary-scan synthesis, BIST (Built-In Self-Test) for embedded memories,
DFT rule checking and automatically integrating the DFT-ready blocks into
DFT-PRO Plus contains VirtualScan, for scan
insertion and compressed ATPG with VirtualScan capability to generate
XtremeCompact scan test patterns. This reduces the cost of semiconductor
testing by a factor of 5x to 50x through reduced test data volume, test
run time and ATE reloads. Users do not need to change their scan methodology.
VirtualScan also works with netlists that have scan inserted using
other popular scan-synthesis tools.
The DFT rule checker identifies almost 100% of DFT violations, at the
RTL stage itself. It also has linting capability. The pre-logic synthesis
identification of RTL design errors averts post-synthesis surprises, which
result in costly and time-consuming redesign iterations. It also enables
reusability of the clean, testable RTL code. Further, most DFT violations
can be repaired automatically.
"The ability to perform DFT audit, scan repair and synthesis at RTL is
a major milestone for SoC designers. They do not have to worry about DFT
issues at a later stage any more," remarked Ravi Apte, senior vice
president for strategy and business development at SynTest. "Further,
the inclusion of VirtualScan, the patent-pending pattern compaction suite
for test cost reduction, in DFT-PRO Plus would make it easy
not only for emerging companies to invest in DFT right from the ASIC/SoC
design start, but also for large IDMs to recover their investment in the
very first design."
Pricing and Availability
Introductory US price till September 30, 2003, for a 3-year time-based
license, DFT-PRO Plus at $159,000.00 and VirtualScan at
The DFT-PRO Plus is available for shipment.
SynTest Technologies, Inc., est. 1990, develops and markets advanced Design-for-Test
(DFT) and Design-for-Debug/Diagnosis (DFD) tools throughout the world,
to semiconductor companies, system houses and design service providers.
The Company's products improve an electronic design's testability
and fault coverage and result in reduced defect levels and reduced slippage
in Time-to-Market (TTM). They also reduce overall design and test costs,
by helping to reduce design iterations as well as the time and reloads
on Automatic Test Equipment (ATE). These products include tools for logic
BIST, memory BIST, boundary-scan synthesis, DFT testability analysis,
VirtualScan synthesis and ATPG with XtremeCompact. test vectors, concurrent
fault simulation, silicon debug and diagnosis.
The company headquartered in Sunnyvale, California, has offices in Taiwan,
Korea and Japan, and distributors in Europe and Asia including Israel.
More information is available at www.syntest.com.
SynTest Technologies Inc. is headquartered at 505 South Pastoria Ave.,
Suite 101, Sunnyvale, California 94086, Phone: 408-720-9956, E-Mail: firstname.lastname@example.org
ASIC: Application Specific Integrated Circuits
ATE: Automatic Test Equipment
ATPG: Automatic Test Program Generation
BIST: Built-In Self-Test
IDM: Integrated Device Manufacturer
RTL: Register Transfer Level
DFT-PRO Plus, VirtualScan and XtremeCompact are trademarks of SynTest
Technologies. All other company or product names are the registered trademarks
or trademarks of their respective owners.