3MTS and SynTest Announce - Step-X

Compact, Low-cost DFT ATE incorporates VirtualScan
To Provide Structural and Functional Instrumentation On Single Platform

Anaheim, June 2, 2003 -- 3MTS, Inc. of San Jose, California, and SynTest Technologies, Inc., of Sunnyvale, California, today announced the new Step-X DFT-ATE system, a new compact, low-cost tester, with design-for-test (DFT) capability. It combines 3MTS' expertise in cost efficient test technology with SynTest's VirtualScana technology, featuring extreme compaction of scan test data.

Step-X directly integrates the DFT VirtualScan environment with 3MTS' configurable ATE in a closed loop solution, enabling users to achieve very high fault coverage, while saving time and cost at all steps in the semiconductor testing process.

The compact Step-X provides a hardware platform for SynTest's VirtualScan technology, to test low cost, high volume devices using a large number of scan chains, but using only a small number of scan test pins on the ATE. Further, using a large number of short scan chains reduces required ATE time. Without compromising product quality, the VirtualScan ATPG generates a very low number of XtremeCompacta test patterns. Hence, very small ATE memory capacity is required.

The VirtualScan technology, uses a proprietary, patent-pending circuitry, on- or off-chip, to broadcast each external scan-input chain to a user-selectable large number of internal scan chains and at the other end, compact them into the original number of external scan-output chains. Step-X provides a hardware platform to house the broadcaster and compactor circuitry external to the chip. Thus, to avail of the benefits of VirtualScan's extreme scan test data compaction, the original chip design does not need to be modified.

"VirtualScan has been designed to compact scan test data more effectively than any other systems. In the new Step-X solution, it works with our reconfigurable 3M20 ATE in design verification, failure analysis, production testing and other applications to dramatically reduce total cost and test time, with minimal memory requirements," said Bill Bottoms, 3MTS founder and chairman.

The 3M20 Low Cost Mixed Signal Test System from Third Millennium Test Solutions is designed to test the integrated analog and digital functions that together comprise the growing list of SOC ICs worldwide. The 3M20 ATE system is customer reconfigurable and enables device-specific tester configuration matching the test system to device test requirements to achieve the lowest possible cost. The 3MTS architecture encompasses both software and hardware, with 3MTS proprietary components integrated tightly with industry standard components.

SynTest's VirtualScan is ideal for applications where scan chains are very long, or in which test hardware is reaching its scan chain limits or test pattern memory is limited.

"We are very happy to be working with 3MTS and to announce Step-X," said Ravi Apte, senior vice president for strategy and business development at SynTest. He added, "In our effort to help customers curb semiconductor testing costs, with Step- X they can now avail themselves of the benefits of VirtualScan's extreme scan test data compaction, without having to modify their chip design. Thus even existing chips with scan chains can be tested using VitrtualScan."

About SynTest:
SynTest Technologies, Inc., est. 1990, develops and markets advanced Design-for-Test (DFT) and Design-for-Debug/Diagnosis (DFD) tools throughout the world, to semiconductor companies, system houses and design service providers. The Company's products improve an electronic design's testability and fault coverage and result in reduced defect levels and reduced slippage in Time-to-Market (TTM). They also reduce overall design and test costs, by helping to reduce design iterations as well as the time and reloads on Automatic Test Equipment (ATE). These products include tools for logic BIST, memory BIST, boundary-scan synthesis, DFT testability analysis, VirtualScan synthesis and ATPG with XtremeCompacta test vectors, concurrent fault simulation, silicon debug and diagnosis.

The company headquartered in Sunnyvale, California, has offices in Taiwan, Korea and Japan, and distributors in Europe and Asia including Israel.
SynTest Technologies Inc. 505 South Pastoria Ave., Suite 101, Sunnyvale, CA 94086, Phone: 408-720-9956, E-Mail: info@syntest.com, Web: www.syntest.com.

Third Millennium Test Solutions (3MTS) is an emerging leader in open architecture, configurable, ATE systems. Headquarters are at 2160 Lundy Av., San Jose, Calif., tel. 408-435-1788. Web: www.3mts.com

Acronyms:
ASIC: Application Specific Integrated Circuits
ATE: Automatic Test Equipment
ATPG: Automatic Test Program Generation
BIST: Built-In Self-Test
DFT: Design-for-Test
DFD: Design-for-Debug/Diagnosis
IDM: Integrated Device Manufacturer
RTL: Register Transfer Level
SoC: System-on-Chip

DFT-PRO Plus, VirtualScan and XtremeCompact are trademarks of SynTest Technologies. All other company or product names are the registered trademarks or trademarks of their respective owners.