SynTest Establishes SynTest Japan Ltd.
New Technical Support
Center to provide greater support to SynTest's growing customer base
Japan and Sunnyvale, California, USA - July 2, 2002 - SynTest Technologies,
Inc., the leading supplier of DFT (Design For Test) tools and services
for SOC (System On Chip) announced that the Company has opened a technical
support center in Shin-Yokohama, as SynTest Japan Ltd.
SynTest's products improve an electronic design's testability and fault
coverage and result in not only reduced defect levels with lower tester
time, but also reduced slippage in time-to market.
"Japan has always been an important market for us, remarked Dr. L.-T.
Wang, SynTest President and CEO.
"We firmly believe that technical support is an important pillar
of our success. Because of the continued and growing interest in our test
tools and services, expanding our technical support resources, was a logical
Leading Japanese electronics companies that are SynTest's customers include
Fujitsu, Mitsubishi, NEC, OKI, Sanyo, SONY and Toshiba among others.
Open House in Shin-Yokohama
SynTest's Technical Support Center is located in the Shin-Yokohama Town
Building 8F, RM802, 3-19-11, Shin-Yokohama Kohoku-Ku, Yokohama-Shi, Japan.
An open house is scheduled in Shin- Yokohama on Friday, July 12, 2002,
from 15:00-17:00. For more information contact Xiaoqing Wen, email@example.com.
About SynTest's Products
SynTest's products include: memory and logic BIST insertion tools; boundary-scan
synthesis tools; DFT integration tools; DFT testability checkers; scan
synthesis and ATPG tools; and a fast concurrent fault simulator. SynTest
also offers a line of products operating on Linux-based PCs for DFD (Design
For Debug/Diagnosis), consisting of SOC and PCB debuggers for improving
SOC and PCB test and debug.
SynTest Technologies, Inc. develops and markets DFT and fault simulation
software tools and offers consulting services throughout the world to
semiconductor companies, ASIC designers and test groups. The Company's
products improve an electronic design's testability and fault coverage
and result in not only reduced defect levels and costly tester time,
but also reduced slippage in time-to-market. For more information, please
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their respective owners.
For Immediate Release
Press Contact:Georgia Marszalek, ValleyPR for SynTest, 650-345-7477