SynTest Expands Its Electronic Design
Debugging Product Line,
Introduces TurboDebug For SOC MEMORY-BIST DEBUG
TurboDebug-SOC/Memory locates and diagnoses faults in embedded SOC
User-friendly software runs on a PC, Annotates debug results on PC display
New Orleans, Louisiana, June 10,
2002 . Design Automation Conference --SynTest Technologies, Inc.(Sunnyvale,
California), the leading supplier of DFT (Design-for-Test) tools and
services for SOC designs today announced TurboDebug-SOC/Memory,
the second member of its Design for Debug/Diagnosis (DFD) product line.
TurboDebug-SOC/Memory reduces the cost of test and debug for SOCs with
large BISTed embedded memories and is being demonstrated this week at
the Design Automation Conference here at booth #1954.
Ravi Apte, Vice President of Marketing and Business Development at SynTest,
noted, "We are all about reducing the cost of test. Our new TurboDebug
product adds the ability to design and debug SOC memory, when using
a BIST methodology. It further expands our DFD product line from PCB
debugging to embedded memory debugging."
TurboDebug-SOC/Memory debugs and diagnoses failures on large embedded
memories. It tests and debugs BISTed embedded SRAM/ROM memory on ASICs/SOCs.
It enables users to detect memory failures down to the bit level. The
testing and diagnosis is easy to perform using pull-down menus. Error
types and locations of the errors are displayed on the PC screen.
The Problem SynTest's TurboDebug-SOC/Memory Solves
Today ASICs/SOCs demand more embedded memories than ever before. More
than 30% of premium space and 50% of the transistors could be allocated
to memory alone, and the memory blocks can be located at physically
diverse locations in the circuit. This mandates that to ensure reduced
failure rates and increased quality, the embedded memories be tested
thoroughly. Built-In Self-Test (BIST) for memories is a solution that
has rapidly become popular.
More about SynTest's TurboDebug Product Line
TurboDebug-SOC/Memory operates on a PC that has a PCI slot and
runs Linux. All communication between the PC and the chip-under-test
is via boundary scan (JTAG) connections. It comes with an interface
board that plugs into the PCI-slot of a PC, and a demo system board.
For testing, users connect the PC-based interface board via a 9-pin
or a 25-pin DB connector to boundary scan pins (TDO, TDI, TCK, TMS and
TRST) on the user's system board.
TurboDebug-PCB, introduced last year at the International Test
Conference, includes the software and hardware needed to debug test
problems on prototype PCBs prior to expensive, time-consuming, full
production testing. It detects, diagnoses and locates interconnect (wiring)
faults on PCBs populated by one or more IC or SOC.
Price and Availability
TurboDebug-SOC/Memory is available for beta testing now. Production
units will ship end of 2002. Pricing for SynTest's TurboDebug product
line starts at $50,000(USD). SynTest's TurboDebug products run on Linux.
SynTest Technologies, Inc. develops and markets DFT and fault simulation
software tools and offers consulting services throughout the world to
semiconductor companies, ASIC designers and test groups. The Company's
products improve an electronic design's testability and fault coverage
and result in not only reduced defect levels and costly tester time,
but also reduced slippage in time-to-market.
SynTest's DFT products include: memory BIST for testing embedded memories;
logic BIST for "at-speed" testing of logic blocks; a boundary-scan
(JTAG) test suite; a DFT integration tool suite; DFT testability checkers
for RTL and gate-level netlists; a partial-scan and full- scan synthesis;
and ATPG tool suite and a super-fast concurrent fault simulator. For
more information visit, www.syntest.com.
ASIC: Application Specific IC
ATPG: Automatic Test Pattern Generator
BIST: Built In Self-Test
DFD: Design for Debug/Diagnosis
IC: Integrated Circuits
JTAG: Joint Test Action Group
PC: Personal Computer
PCB: Printed Circuit Board
RTL: Register Transfer Level
TurboDebug is a
trademark of SynTest Technologies, Inc. All other trademarks are the
property of their respective owners.
For Release June 10, 2002
Design Automation Conference Booth Number 1954
Georgia Marszalek, ValleyPR for SynTest, 650-345-7477, email@example.com