Bay Microsystems Delivers 10Gbps Network Processor Developed with SynTest's DFT Tools

SynTest Tools and Services Helped Bay Microsystems Capitalize on Market Window Opportunity, and Speed-Up the Introduction of the Industry's First Single-chip OC192/10G Network Processor and Traffic Manager

SUNNYVALE, California, June 5, 2002-- Bay Microsystems, Inc., a privately held, fabless
communication IC company, recently announced First Customer Ship (FCS) of its "right first time" 10 Gigabit per second Montego™ Internetworking Processor using SynTest's DFT tools and services. This ultra-high performance packet-processing device was implemented using 0.18-micron semiconductor process technology and was completed in record time. This portentous achievement resulted from an accelerated bring up time, facilitated by the DFT tools supplied by SynTest Technologies, Inc (, a Sunnyvale, Calif.-based DFT software tool and services company.

With the release of Montego, Bay Microsystems has created a new class of network processor that combines scalability, intelligence processing and ultra-high performance in highly integrated single chip solutions, that scale from "Access to Long Haul." SynTest's tools and services proved invaluable by improving testability and reducing test time, thereby enabling Bay to meet its aggressive market window for release.

Tony Chiang, Vice President of Engineering at Bay Microsystems said, "We are very happy with our choice of SynTest, as our DFT partner. By providing exemplary DFT services, and installing their tools at our site, they enabled us to test various modules on command, drastically reducing down time and maximizing our productivity. The compact ATPG patterns generated by SynTest's TurboScan-ATPG software allowed us to reduce time-to-market . using ATE to test the structural reliability of our chip design."

Dr. L.T. Wang, President, SynTest, "We would like to congratulate Bay Microsystems, Tony
Chiang and his team, on their stellar achievement. We are very honored and happy that Tony put his confidence in SynTest and that we were able to contribute to their success.

How Bay Used SynTest's DFT Tools and Services

To ensure a predictable outcome and eliminate potential design flaws at the last minute, and to achieve high fault coverage, Bay Microsystems chose to use DFT methodology for a scan-based design from the very beginning. It selected SynTest's TurboScan™ scan insertion and ATPG tool, and SynTest's services, as well as SynTest's Turbo BSD™, for boundary scan synthesis, to facilitate the testing of its memory BIST and full scan chains on multiple-linked modules. Tony Chiang noted, "With the goal of minimizing the drain on our internal resources, we decided to look for a partner with a complete set of proven and easy-to-use DFT tools, who could support our efforts.

"Our primary concern was to take action up front to detect errors and to avoid costly and timeconsuming mistakes, down the road. It was crucial not to get bogged down with lots of debugging after the chip had taped out. We would lose the valuable time gained by using a modular approach. The chip was going to be complex and huge and we knew that functional tests would not be adequate and reliable. We had to have high fault coverage and compact ATPG patterns. SynTest helped our stellar design team achieve our goals."

About Bay Microsystems, Inc.

Bay Microsystems Inc. is a privately held, fabless communication IC company. Bay's
Internetworking Processor (InP) Family™ of programmable packet processing devices combines scalability, intelligence processing and ultra-high performance in highly integrated solutions. These devices are ideally suited to scale from "Access to Long Haul" for carrier class products such as access concentrators, voice, wireless and xDSL gateways, multi service switches and routers, cable head ends and intelligent optical (DWDM, Sonet) transport equipment, deployed within the metroedge, metro-core, regional and long-haul markets. The InP Family includes the industry's first single chip OC192c/10G Network Processor/Traffic Manager with switching.

Bay's highly experienced management and world-class engineering team have three generations of proven expertise in architecture, implementation, deployment, marketing and management of network processors. Bay Microsystems is a member of the Optical Internetworking Forum (OIF), Network Processor Forum (NPF), MPLS and ATM forums and actively participates in the IETF. For more information visit the website at

About SynTest

SynTest Technologies, Inc. develops and markets DFT and fault simulation software tools and
offers consulting services throughout the world to semiconductor companies, ASIC designers and test groups.
The Company's products improve an electronic design's testability and fault coverage and result in not only reduced defect levels and costly tester time, but also reduced slippage in time-to-market.

SynTest's DFT products include: memory BIST for testing embedded memories; logic BIST for "at-speed" testing of logic blocks; a boundary-scan (JTAG) test suite; a DFT integration tool suite; DFT testability checkers for RTL and gate-level netlists; a partial-scan and full- scan synthesis; and ATPG tool suite and a super-fast concurrent fault simulator. For more information visit,

ATE: Automatic Test Equipment
ATPG: Automatic Test Pattern Generation
BIST: Built-In Self-Test
DFT: Design-for-Test
IC: Integrated Circuit

TurboBSD and TurboScan are trademarks of SynTest Technologies, Inc.
Bay Microsystems, Internetworking Processor, Montego, NEXTware and AnyMapping are trademarks of Bay Microsystems. All other company names are trademarks of their respective holders.

For Release June 10, 2002 Design Automation Conference Booth Number 1954
Press Contact:
Georgia Marszalek, ValleyPR for SynTest, 650-345-7477,