SYNTEST TEAMS WITH TSMC TO IMPROVE SoC TESTABILITY

Alliance Reduces Tester Time, Improves Chip Quality for TSMC's Customers, Includes Turnkey and DFT Services

SUNNYVALE, California - October 10, 2001 - SynTest Technologies, Inc., the leading supplier of DFT (Design-for-Test) services for SoC designs, announced today that it is now a member of Taiwan Semiconductor Manufacturing Company's (TSMC's) Design Center Alliance. SynTest will collaborate with TSMC to provide DFT and full turkey services for designers of complex System-on-Chip (SoC) designs.

The DCA alliance gives TSMC's customers proven resources for improving SoC design quality. SynTest offers TSMC's foundry customers DFT and full turnkey services that reduce overall test costs and result in cost-effective prototype and production chips.

Andley Chang, program manager of design services marketing for TSMC said, "as the global semiconductor industry moves towards 0.10-micron semiconductor manufacturing processes for their single-chip systems, they require a wider range of support, including design and testability services. SynTest's services have been used successfully by our customers for some time, confirming our earlier decision to make them our first Design Center Alliance partner for DFT.

Dr. L.T. Wang, president of SynTest added, "Our goals are to improve circuit testability and reduce the cost of test and debug. Today, most of our customers verify their products on TSMC silicon. As a result of working with TSMC and its customers, we have the proven DFT solutions that are necessary to provide the highest possible circuit and system testability for TSMC processes. We are very pleased that together with TSMC, we can provide customers with full turnkey services, in addition to our proven design for test services."

About TSMC

TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced 300mm wafer fabs, six eight-inch fabs and two six-inch wafer fabs. TSMC also has substantial capacity commitments at two joint ventures fabs (Vanguard and SSMC) and at its wholly-owned subsidiary, WaferTech. In early 2001, TSMC became the first IC manufacturer to announce a 0.10-micron technology alignment program with its customers. TSMC's corporate headquarters are in Hsin-Chu, Taiwan. For more information about TSMC see http://www.tsmc.com.

About SynTest

SynTest Technologies, Inc. provides semiconductor companies, SoC designers and test groups with full turnkey services, which include physical design, prototype development and debug, final test, prototype sample delivery, supply chain management for production delivery, as well as DFT services and tools.
The company's services and tools improve quality, reduce testing and debug costs, and reduce time-to-market for SoC designs. SynTest's DFT tools include tools for testability checking; logic and memory BIST; boundary scan design; scan insertion, ATPG and fault simulation. For more information, visit www.syntest.com.

Acronyms:
ASIC: Application Specific IC
ATPG: Automatic Test Pattern Generation
BIST: Built-In Self-Test
DFD: Design-for-Debug/Diagnosis
DFT: Design-for-Test
IC: Integrated Circuit
IDM: Integrated Device Manufacturer
IP: Intellectual Property
SoC: System-on-Chip

All tradenames and trademarks are the property of their respective owners.

For Release October 10, 2001
For Information Contact:
Georgia Marszalek, ValleyPR for SynTest, (650) 345-7477 georgia@ValleyPR.com
Daniel J. Holden, TSMC North America, (408) 382-7921, dholden@tsmc.com