Fabless Semiconductor Company, Avalent Technologies, Chooses
SynTest's DFT Tools to Improve Testability of ASICs Used in
Communications, Mobile, Multimedia and Wireless Applications

SynTest's ATPG and BIST Tools Reduce Defect Level and Tester Time for SoCs That Use
Avalent's high-performance, power-efficient, low-cost ASICs

Santa Clara, California, October 10, 2001 -- FSA Suppliers Expo -- Avalent Technologies, Inc. of San Jose, California today announced that it has standardized on DFT tools from SynTest Technologies, Inc. of Sunnyvale, California to improve the testability of SoCs using Avalent's high-performance, high-density ASIC cores.

The SynTest tools allow Avalent licensees to improve testability and fault coverage and reduce defect levels and tester time. Avalent customers are using SynTest's, Turbo-Scan-ATPG(TM) and TurboBIST-Memory(TM) tools to improve their system's testability.

Avalent selected SynTest's TurboBIST for its ASIC embedded memory testing and SynTest's DFT tools for generating design dependent test patterns for manufacturing. For Avalent's ASICs with its reconfigurable architecture and re-programmability, the number of test vectors is reduced significantly. Benchmarks show that for a typical ASIC-based SoC design, there can be more than a 60% reduction in the number of manufacturing test vectors required for 98% test coverage.

"Our goal is to provide our customers with high-performance, power-efficient, low-cost ASIC solutions for their designs. The need to support highly effective testing tools is becoming more important as design complexities increase dramatically and development cycle pressure arises. We are very pleased to have this partnership with SynTest in place and to work with them to jointly develop our ASIC testing capabilities in order to deliver greater value to our customers," said, Herman So, Vice President, Avalent Technologies.

Mr. So added, " SynTest's tools fit very well in the standard ASIC flow used by our customers."

L.-T. Wang, SynTest president, noted, " Avalent has superior technology for advanced ASICs. Their customers have the advantage of using our full scan and memory BIST products to make their designs more testable and reduce their tester costs."

About Avalent Technologies

Avalent Technologies, Inc. develops ASICs for evolving communications, mobile multimedia and wireless applications. Avalent Technologies' system tools and complete SOC designs offer total life-cycle solutions with rapid time-to-market, ease-of-design and low design development cost. Avalent Technologies, Inc. is a privately held fabless semiconductor company based in San Jose, California. For more information, please visit http://www.avalent.com

About SynTest

SynTest Technologies, Inc., develops and markets DFT, logic and memory BIST synthesis, boundary scan, ATPG and fault simulation software tools and offers consulting services throughout the world to semiconductor companies, ASIC designers and test groups. SynTest has offices in Korea, Taiwan and the USA, and distribution partners in Canada, Israel, France, Italy, the UK, Japan and Singapore.

Acronyms:
ASIC: Application Specific Integrated Circuit
ATPG: Automatic Test Pattern Generation
BIST: Built-in Self-test
DFT: Design-for-Test
IP: Intellectual Property
SOC: System-on-Chip


TurboBIST-LOGIC, TurboBIST-Memory, and TurboScan are trademarks of SynTest Technologies, Inc. All other trademarks are the property of their respective owners.

For Release October 10, 2001 at Fabless Semiconductor Association Suppliers Expo
Press Contacts:
Herman So, Avalent Technologies, Inc., 408-435-1188 x103, herman@avalent.com
Georgia Marszalek, ValleyPR for SynTest, 650-345-7477, georgia@valleypr.com