SynTest INTRODUCES LOGIC BIST TOOL

99% fault coverage possible with SynTest's DFT tools
LG Electronics of Korea among the first customers

MUNICH, Germany and SUNNYVALE, Calif., USA-March 12, 2001-DATE Conference-SynTest Technologies, Inc. (Sunnyvale, CA, USA), the leading supplier of DFT (Design-for-Test) tools and services for integrated circuit designers and foundries, today announced a logic BIST (Built-In Self Test) tool--TurboBIST-Logic™--for Verilog and VHDL designs. TurboBIST-Logic includes SynTest's proven scan ATPG technology and can be used with SynTest's boundary scan and memory BIST products to achieve 99% plus fault coverage. SynTest also announced that LG Electronics, Inc. (Korea) is using TurboBIST-Logic for at-speed testing.

TurboBIST-Logic reduces test development time and costs, as well as time-to-market, by simplifying the implementation of a complete test solution. It enables at-speed testing for multi-frequency, multi-clock logic circuits such as intellectual property (IP) blocks or complete Systems-on-Chips (SoCs). Its use results in higher quality tests and lower defect rates.

LG uses Turbo-BIST at-speed

"For our complex multimedia SoC designs of around 4 million gates with clock speeds of up to 108 MHz, we found that delay faults are the origin of most of test escapes," notes Mr. Boik Sohn, Business Operations manager, System IC Business, LG Electronics. "TurboBIST-Logic with its smart sequential ATPG engine is a solution for this problem because it allows us to do at-speed test with higher fault coverage for both delay faults and stuck-at-faults."

What SynTest says

"The trend today is to design increasingly complex SoCs that include intellectual property from various sources," remarked L.-T. Wang, SynTest Technologies' president. "This brings with it the challenge of providing optimum test schemes in terms of methodologies, coverage, time and cost."

Wang continued. "Testing at true operational speed has become essential for complex sub-micron chips, where path delays and timing faults are crucial to their operation. Only full-clock speed or at-speed testing can discover these. TurboBIST-Logic offers the ability to test a circuit at its full-operating speed. This is not possible using scan-based ATPG alone; and combining BIST with our scan-based ATPG fault coverage tool can boost total fault coverage to over 99%."


More about SynTest's TurboBIST-Logic Product

TurboBIST-Logic checks for and automatically repairs most BIST violations.
It enables at-speed testing of multiple-frequency clock domains, which is crucial for extremely large and complex designs. It also captures multiple scan signals within a single clock cycle, and offers concurrent testing of all clocks in the circuit.

Higher fault coverage is achieved by TurboBIST-Logic's integration of SynTest's sequential ATPG technology for full-scan and partial-scan. This integration limits the number of iterations required and the overhead related to test point insertion.

TurboBIST-Logic can be used with SynTest's boundary-scan tool, TurboBSD and memory BIST tool, TurboBIST-Memory;, to implement SoC level testability schemes, enabling comprehensive board and system level test during manufacturing and in the field.

Availability

TurboBIST-Logic is available now for LINUX and UNIX workstations from Sun Microsystems (NASDAQ: SUNW) and Hewlett Packard (NASDAQ: HPW).
SynTest also offers DFT insertion services for memory, logic and core testing.

About SynTest's DFT Products:

SynTest's DFT products include TurboBIST-Memory for memory testing, TurboFCE&, a fault coverage estimator, TurboBSD, a boundary-scan test suite; TurboCheck, design and testability checkers for RTL and gate-level netlists; and TurboScan, a partial-scan and full- scan synthesis and ATPG program. SynTest also offers TurboFault, a super-fast, concurrent fault simulator.

About SynTest

SynTest Technologies, Inc. develops and markets DFT and fault simulation software tools and offers consulting services throughout the world to semiconductor companies, ASIC designers and test groups.
The Company's products improve an electronic design's testability and fault coverage and result in not only reduced defect levels and costly tester time, but also reduced slippage in time-to-market.

SynTest has offices in Korea, Taiwan and the USA and distribution partners/representatives in Canada, Israel, France, Italy, the UK, Japan and Singapore.

Contacts for Reader Inquiries:

SynTest Technologies, Inc., 505 S. Pastoria Ave, Suite 101, Sunnyvale, CA 94086, USA, www.SynTest.com
Tel: 1-408-720-9956, Fax: 1-408-720-9960, info@SynTest.com, Attn: Nayan Pradhan

Acronyms and definitions:

ASIC: Application Specific Integrated Circuit
ATPG: Automatic Test Pattern Generation
BIST: Built-in Self-test
Delay Fault: A fault caused due to the impedance of the path carrying the signal, resulting in an undesirable delay
DFT: Design-for-Test
EDA: Electronic Design Automation
HDL: Hardware Description Language
IC: Integrated Circuit
IP: Intellectual Property
RTL: Register Transfer-Level (a design description above gate-level netlists)
SoC: System-on-Chip
VHDL: VHSIC (Very High-Speed Integrated Circuit) HDL

TurboBIST-LOGIC, TurboBIST-Memory, TurboBSD, TurboCheck, TurboFault, TurboFCE and TurboScan are trademarks of SynTest Technologies, Inc. All other trademarks are the property of their respective owners.

For Information Contact:
Georgia Marszalek, ValleyPR for SynTest, (650) 345-7477, georgia@valleypr.com