SynTest Adds VHDL Capability
To Its RTL Testability Analysis Tool Suite

TurboCheck-RTL now available for VHDL and Verilog

Paris, France and Sunnyvale, CA, USA, DATE Conference March 27, 2000--SynTest Technologies, Inc. (Sunnyvale, CA), an EDA company and supplier of DFT tools for IC designers and foundries, announced today that the company is introducing a VHDL version of its popular TurboCheck™, an RTL design and test rule violation checker.

The VHDL product extends SynTest's testability analyzer tool suite for improving a designs testability and fault coverage from Verilog to VHDL. TurboCheck analyzes the testability of combinational and sequential circuits and reports on signal controllability and observability characteristics that are most likely to affect the circuit's final fault coverage and tester time.

L.-T. Wang, SynTest Technologies' president, said, "Our goal has always been to provide a complete DFT solution to our customers. Because of the market acceptance of both Verilog and VHDL throughout the world, we are adding VHDL to support our expanding customer base in Europe."

TurboCheck-RTL for Verilog VHDL

SynTest's Turbo-Check supports either Verilog or VHDL, depending on the version selected, before synthesis and verification and simulation.

TurboCheck-RTL checks for design as well as test rule violations at the RTL and verifies whether the RTL design is synthesizable by popular synthesis tools, such as those from Synopsys and Cadence Design Systems.

It identifies testability problems early in the design cycle. Removing these problems at the RTL stage reduces design iterations, improves test insertion, Automatic Test Pattern Generation(ATPG), and fault coverage.

TurboCheck identifies most test rule violations, such as combinational feedback loops, generated clocks, gated clocks, asynchronous set and reset and floating busses.

TurboCheck provides more thorough checking than most other solutions, since it separates generated clocks from gated clocks and checks whether embedded RAMs or flip-flops and latches are accessible or initializable from primary input pins.

Pricing and Availability

TurboCheck-RTL for VHDL is available now for UNIX workstations, including the Sun OS and Sun UltraSPARC. TurboCheck-RTL is priced at $35,000 (USD) in the USA and $ 43,750 (USD)
internationally. A Verilog version is also shipping now and priced similarly.

About SynTest

SynTest Technologies, Inc. was founded in 1990 and is headquartered in Sunnyvale, CA, USA with offices in Japan, Taiwan and Korea. The company develops and markets DFT, logic and memory BIST synthesis, boundary scan, ATPG and fault simulation software tools and offers consulting services throughout the world to semiconductor companies, ASIC designers and test groups.

SynTest's products include TurboBIST, a boundary-scan test suite; TurboCheck, a gate-level and RTL design and testability analyzer; TurboFault, a fast fault simulator; and TurboScan, a full-scan and partial-scan synthesis and ATPG program.

Contact for Reader Inquiries

SynTest Technologies, Inc., 505 S. Pastoria Ave, Suite 101, Sunnyvale, CA 94086, USA,
408-720-9956, Fax: 408-720-9960, www.syntest.com, Attention: Jongsup Baek

Notes to editors

Graphic available on request.

Acronyms

ASIC: Application Specific Integrated Circuit
ATPG: Automatic Test Pattern Generation
BIST: built-in Self-Test
DFT: Design-for-Test
EDA: Electronic Design Automation
HDL: Hardware Description Language
IC: Integrated Circuit
RTL: Register Transfer-Level

urboBIST, TurboBSD, TurboCheck, TurboFault and TurboScan are trademarks of SynTest Technologies, Inc.
All other trademarks are the property of their respective owners.

For Immediate Release DATE booth number 114
For Information Contact:
Georgia Marszalek, ValleyPR for SynTest, (650) 345-7477, georgia@valleypr.com