SynTest UNVEILS PLANS FOR INTEGRATED EXPERT DFT TOOL SUITES FOR DSM AND NETWORKING APPLICATIONS

TurboScan-Ready and TurboDFT-Ready Tool Bundles Are Shipping Now
Integrated SOC DFT Tool Bundles will be announced next year

Sunnyvale, CA, USA, November 23,1999 ---SynTest Technologies, Inc., an EDA Company and DFT tool supplier, today announced that it plans to integrate several of its popular DFT tools next year and as a first step SynTest is bundling several of its DFT tools in two user-specific packages -- TurboScan-Ready and TurboDFT-Ready --to provide more value to designers who use deep submicron (DSM) (below .18 micron) technology and are involved with designing networking applications.

The DFT suites offer improve system-on-chip (SOC) testability.

SynTest's DFT tools improve electronic product reliability and quality, and reduce manufacturing test time.

According to L.-T. Wang, SynTest president, "The new bundles address the needs of designers doing networking designs or targeting deep submicron technologies. They are the first steps in our plan to fully integrate our DFT tools so designers can achieve full testability for their SoCs."

The TurboScan-Ready suite offers automatic scan selection, repair, reordering and debug capabilities for multiple clock domain designs. These features are unavailable with other scan synthesis tools.

The TurboScan-Ready suite works with popular synthesis tools like Cadence Design Systems' Envisia Ambit tool, and complements them by adding gate-level design analysis and scan synthesis technology. It includes:

The TurboDFT-Ready suite includes:

Wang, noted, "Networking and telecommunications companies in particular find the TurboDFT-Ready bundle attractive since they often include these test features in their designs to attain their quality goals."

"With TurboCheck-RTL, designers do not have to wait until after synthesis to find scan rule violations. This capability alone can save days in the design cycle by reducing or eliminating logic synthesis iterations."

TurboBSD automatically generate synthesizable Verilog or VHDL code with race-free operation between the test clock line and the boundary scan chain. It includes features for extracting existing boundary scan chain information, if any, and generates private test benches, including BIST instructions and phase-lock loop (PLL) tests.

TurboBIST-SRAM reduces the time and effort required for design, test development and testing of embedded single and dual-port RAMs, and improves production quality. It also synthesizes SRAM BIST structures for any user-specified test algorithms.

SynTest's boundary scan synthesis customers report reductions from three to four weeks to only a few hours in the time it takes to synthesize boundary scan cells and the TAP controller, do ATPG and generate the Boundary Scan Description Language (BSDL) file. The RTL testability analysis provides pre-synthesis DFT rule checking and reduces the number of synthesis iterations. The automatic testabilityproblem repair capability in the scan synthesis tool allows the ATPG engine to generate more compact, higher fault coverage test vectors in less time than similar tools from other suppliers.

Pricing and Availability

Both tool suites are available now for UNIX workstations. Pricing for the TurboScan-Ready bundle is $37,500 (USD); the TurboDFT-Ready bundles is $75,000 (USD)

SynTest is offering tokens each good for one license per month with the purchase of these DFT bundles to allow customers to use its advanced DFT and BIST technology at a very low cost.

Wang, noted, "We are aggressively pricing our tools at less than half their list prices with tokens for our other tools, so users have the advantage of using all our tools within their current design environments."

About SynTest SynTest

Technologies, Inc. develops and markets DFT software tools and offers consulting services throughout the world. SynTest's products improve a design's testability and fault coverage and result in reduced defect levels and tester time.

SynTest has over 100 customers worldwide, including semiconductor companies, ASIC designers and test groups.

SynTest Technologies, Inc. is headquartered at 505 S. Pastoria Ave, Suite 101, Sunnyvale,CA 94086, USA, 408-720-9956, Fax: 408-720-9960, info@SynTest.com,

Contact for Reader Inquiries

SynTest Technologies, Inc., 505 S. Pastoria Ave, Suite 101, Sunnyvale, CA 94086, USA, 1-408-720-9956, Fax: 408-720-9960, info@SynTest.com, www.SynTest.com,

Notes to editors

Graphics available on request.

Acronyms and definitions

ASIC: Application Specific IC
ATPG: Automatic Test Pattern Generation
BIST: Built-in Self-test
BSDL: Boundary Scan Description Language
DFT: Design-for-Test
EDA: Electronic Design Automation
HDL: Hardware Description Language
IC: Integrated Circuit

Private test benches: codes users write to test private IEEE-STD-1149.1 functions that they have included in their chips that are accessible via a TAP controller.

RTL: Register Transfer-Level (a design description above gate-level netlists)
SRAM: Static RAM
TAP: Test Access Port

Token: represents the right to use the license for one tool for one month.

VHDL: VHSIC (Very High-Speed Integrated Circuit) HDL

TurboBIST-SRAM, TurboBSD, TurboCheck and TurboScan are trademarks of SynTest Technologies, Inc.
All other trademarks are the property of their respective owners.

For release November 23, 1999