LG Semicon Licenses Its HDL Logic Simulator to SynTest Technologies

SynTest plans to use the simulator to add an RTL fault simulator to its product line;

Sunnyvale, CA, USA and Seoul, Korea?January 18, 1999?SynTest Technologies, Inc. (Sunnyvale, CA, USA), an EDA Company and supplier of DFT tools for IC designers and foundries, and LG Semicon announced today that SynTest has licensed the source code for LG Semicon's Verilog hardware description language (HDL) simulator. The value of the agreement was not disclosed.

This agreement allows SynTest to add a higher-level (or Register Transfer- Level (RTL)) fault simulator to its product line. SynTest currently offers TurboFault™, a fast gate-level software fault simulator.

SynTest's products improve a design's testability and fault coverage and result in reduced defect levels and tester time.

Dr. Seong Hong, Managing Director of LG Semicon, noted, "Our engineers evaluated SynTest's gate-level fault simulator, TurboFault, and compared the results to those from another commercial fault simulator we purchased a few years ago. We found TurboFault ran more than 100 times faster --6 hours vs. 5 days with 10% sampling-- with similar fault coverage results. This prompted us to add TurboFault to our design flow. Since some of our designs contains RT-level representations, we hope to add SynTest's RTL fault simulator later this year."

Dr. Sung-Ho Kang, Executive Vice-president of LG Semicon, further added, "We licensed our HDL simulator to SynTest because we hope to take advantage of using Syntest's RTL fault simulator with other SynTest DFT products in our DFT flow."

According to L.-T. Wang, SynTest Technologies' president, "DFT analysis is done more and more at the RT-level. In order to maintain our position as the leading supplier of a complete set of DFT tools, we are always looking for ways to improve and add to our product line. LG Semicon's HDL simulator will allow us to add RT-level fault simulation."

Wang, noted, "We plan to announce a RT-level fault simulator later this year."

SynTest's RT-level products include TurboFCE™, a fault coverage enhancer, and TurboCheck™, a design and testability analyzer. These products work with popular RT-level fault simulators.

As well as TurboFault, SynTest  8  88  8  888  8  88  8  8888other gate-level products include TurboBSD ™a boundary-scan test suite; TurboCheck, a design and testability analyzer; and TurboScan™, partial-scan and full- scan synthesis and ATPG program.

SynTest's¡ Ð products are available for UNIX platforms. Windows NT versions of SynTest's TurboFCE, TurboCheck and TurboFault were introduced last year (10/19/98).

About SynTest:

SynTest Technologies, Inc. was founded in 1990 and is headquartered in Sunnyvale, CA, USA with offices in Japan, Taiwan and Korea. The Company develops and markets DFT software tools and offers consulting services throughout the world. SynTest has over 80 customers, including semiconductor companies, ASIC designers and test groups.

Contacts for Reader Inquiries:

SynTest Technologies, Inc., 505 S. Pastoria Ave, Suite 101, Sunnyvale, CA 94086, USA,
408-720-9956, Fax: 408-720-9960, info@SynTest.com, http://www.SynTest.com
Attn: Elisabeth Calder

Acronyms and definitions:

ASIC: Application Specific Integrated Circuit
ATPG: Automatic Test Pattern Generation
DFT: Design-for-Test
EDA: Electronic Design Automation
HDL: Hardware Description Language
IC: Integrated Circuit
RTL: Register Transfer-Level (a design description above gate-level netlists)

TurboFCE, TurboBSD, TurboCheck, TurboFault and TurboScan are trademarks of SynTest Technologies, Inc.All other trademarks are the property of their respective owners.

For release January 18, 1999

For Information Contact:
Georgia Marszalek, SynTest Public Relations Counsel,(650) 345-7477, georgia@valleypr.com