FOR RELEASE June 9, 1997 DAC Booth 1300
For Information Contact:
Georgia Marszalek, SynTest, Public Relations Counsel
(415) 345-7477, FAX: (415) 341-0388, georgia@valleypr.com

www.syntest.com

 

SYNTEST INTRODUCES NEW VERSION OF ITS ATPG TOOL

Customers confirm TurboScan(tm) has better test vector compaction,
achieves higher fault coverage with less silicon, and reduces design and test time by up to 50%

 

Anaheim, CA--June 9, 1997--Design Automation Conference--SynTest Technologies, Inc.,
a supplier and developer of test and verification solutions for integrated circuit (IC) designers and
foundries, is announcing an upgrade to the company¡¯s ATPG product-TurboScan(TM) 2.0.

The latest version of TuboScan adds technology that achieves high fault coverage with reduced
silicon usage, and compacts the test sets to reduce design and tester time from 25% to 50% over
previous versions.

According to L.-T. Wang, SynTest's founder and President, "We continually survey our customers
about what is important to them. For our ATPG customers more compact test vector sets and
better coverage for test methodologies, like partial-scan, that minimize silicon usage, are priorities.

The new version of TurboScan saves simulation time and tester cost by generating more compact
test sets, even for a full-scan design methodology. New technology provides higher fault coverage
with less silicon used for test structures."

What Sony and Chip Express Are Saying About TurboScan:

Takeshi Onodera, Assistant Manager, Sony (Japan), noted, "Silicon reduction is very important to
us, as well as quality and time-to-market. With SynTest's TurboScan, we are reducing silicon
overhead by using a partial-scan strategy, and achieving fault coverage of 99%. It's surprising that
TurboScan performs the highest vector compaction and faster ATPG at the same time."

Ehud (Udi) Yuhjtman, Chip Express¡¯ Director of Engineering and CAE operations (Santa Clara,
CA), added, "Because of the nature of a time-to-market company, Chip Express requires a
push-button solution for our SCAN and ATPG processes. With the help of SynTest and SynTest's
latest tools, Chip Express is achieving 99% fault coverage on designs in the gate range of 60-100K
in less than a week, and sometimes as fast as 1 to 2 days."

New Technology and Benchmark Results:

To improve speed and accuracy, TurboScan 2.0 uses dynamic compaction and a 32-value system
(compared to a 4-value system used previously). This new compaction technology reduces the
backtrack search space, and allows TurboScan to make better decisions for generating more
compact vectors.

A recent customer benchmark for a 215K-gate design achieved 97.97% fault coverage, 99.99%
test efficiency with 160 patterns in 1 hour and 17 minutes running on a Sun UltraSPARC 140.

More about TurboScan:

TurboScan is a sequential and combinational ATPG for gate-level digital designs. It generates test
sets for full-scan, partial-scan, and non-scan designs. TurboScan¡¯s technology results in coverage
of up to 100%. It uses the structural-level Verilog or VHDL netlists or EDIF or TDL netlists as input.
TurboScan handles asynchronous sequential circuits, containing gated clocks, RAMs, ROMs,
tri-state gates, and unidirectional MOS transistors.

SynTest also offers an IDDQ test option useful for wafer sorting.

SynTest¡¯s TurboScan began shipping in 1991.

Pricing and availability:

PICASSO runs on UNIX workstations, including Sun and Sun UltraSPARC. It is shipping now.
The price starts at $85,000 (USD).

SynTest products:

SynTest's products include: its testability analysis tool-TurboCheck; full-scan, partial-scan synthesis
and ATPG-TurboScan; S-RAM and DRAM BIST tool-TurboBIST; boundary scan test tool-TurboBSD;
and TurboFault, the fastest commercially available software fault simulator. All of SynTest¡¯s
products accept the same input formats, and use the same libraries and database.

For information contact:

SynTest Technologies, Inc., 505 S. Pastoria Ave, Suite 101, Sunnyvale, CA 94086, USA,
408-720-9956, Fax: 408-720-9960, info@syntest.com.

SynTest Technologies, Inc. was founded in 1990 and is headquartered in Sunnyvale, CA, USA
with offices in Japan, Korea and Taiwan. The Company develops and markets test and verification
tools and consulting services throughout the world to semiconductor companies and ASIC designers.

SynTest worldwide customers include: Alliance Semiconductor, Chip Express, Cirrus Logic, Cisco,
8X8, Fujitsu, Hyundai, RISE, Oki Semiconductor, Motorola, Orbit Semiconductor, Sony and UMC.

###

Acronyms:

ASIC: Application Specific Integrated Circuit
ATPG: Automatic Test Pattern Generator
BIST: Built-in-Self-Test
EDIF: Electronic Design Interchange Format
HDL: Hardware Description Language
IC: Integrated Circuit
IDDQ: Quiescent VDD supply current
MOS: Metal-Oxide Semiconductor
RAM: Random Access Memory
ROM: Read Only Memory
TDL: Tegas Description Language
VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

Note to editors:
Data sheets, electronic versions of graphics or screen shots are available upon request.

 

TurboScan, TurboCheck, TurboBIST, TurboBSD and TurboFault, SynTest and the company's logo
are trademarks of SynTest Technologies, Inc. All other trademarks are the property of their
respective owners.