Today's ASIC/SOC devices can contain hundreds of memories, several types of logic, dozens of functional blocks obtained from diverse sources, and multiple clocks operating at multiple frequencies. This makes it almost impossible to achieve the level of fault coverage your company expects solely by writing functional vectors. When handling such device designs a proper test strategy needs to be defined to attain the expected level of fault coverage, with optimal test costs and time required for testing.
In such cases, a strong team of design engineers cannot help much, because testability is another issue. Even if you have the budget to bring DFT tools in-house maintaining adequate resources of testability experts in-house is a significant additional expenditure.
It is in such situations that a SynTest DFT consulting services arrangement can provide the greatest benefit. For a specific design, and under your direction, SynTest can step-in to provide the testability expertise to allow you to reach your fault coverage targets. We can work with you throughout the project from design through tape-out to final silicon, with the sole objective of ensuring your success.
