SynTest DFT Consulting Services


Today's ASIC/SOC devices can contain hundreds of memories, several types of logic, dozens of functional blocks obtained from diverse sources, and multiple clocks operating at multiple frequencies. This makes it almost impossible to achieve the level of fault coverage your company expects solely by writing functional vectors. When handling such device designs a proper test strategy needs to be defined to attain the expected level of fault coverage, with optimal test costs and time required for testing.

In such cases, a strong team of design engineers cannot help much, because testability is another issue. Even if you have the budget to bring DFT tools in-house maintaining adequate resources of testability experts in-house is a significant additional expenditure.

It is in such situations that a SynTest DFT consulting services arrangement can provide the greatest benefit. For a specific design, and under your direction, SynTest can step-in to provide the testability expertise to allow you to reach your fault coverage targets. We can work with you throughout the project from design through tape-out to final silicon, with the sole objective of ensuring your success.


  • Attain desired level of quality through increased fault coverage, but with minimum overhead
  • Reduce costs of returns and field replacements
  • Reduce time and costs at the tester through powerful pattern compaction
  • Improve engineering productivity
  • Reduce product time-to-market (TTM)
  • Gain valuable testability experience for future designs

Scope of Services

SynTest provides the following DFT consulting services:

  • Consultation regarding appropriate DFT methodologies for a given design
  • DFT design rule checking and testability analysis
  • Memory BIST insertion
  • Logic BIST insertion
  • Boundary scan (IEEE 1149.1 compliant JTAG) synthesis
  • Scan synthesis (with optional repair capability), and ATPG, including using VirtualScanO to generate XtremeCompactO test data patterns.

    We can also generate ATPG patterns with netlists having scan inserted using third party EDA tools
  • Fault simulation / grading
  • Pattern conversion to serial Verilog testbench for production
  • Written report summarizing results, strategies and additional recommendations

For more information on SynTest DFT products and services,
please call (408) 720-9956 or contact

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