VLSI
Test Principles and Architectures - Design for Testability
(Elsevier July 7, 2006)
A
new ATPG method for efficient capture power reduction during scan testing
(VLSI Test Symposium 2006)
Ultrascan:
using time-division demultiplexing/multiplexing (TDDM/TDM) with virtualscan for
test cost reduction (ITC 2005)
At-speed
logic BIST architecture for multi-clock designs
(Int. Conf. on Computer Design 2005)
At-speed
logic BIST for IP cores (DATE 2005)
VirtualScan:
A New Compressed Scan Technology for Test Cost Reduction
(ITC 2004)
Test
Data Compaction tool from SynTest: VirtualScan Application Story
(Jananese Version) (January 29, 2004)
Design
for life (Test&Measurement World June 1, 2004)
Group
seeks standard for test coverage reports (EE
Times April 26, 2004)
Design-for-test
moves up to RT level (EE Times June 9, 2003)
The
case for logic BIST (EE Times February 14, 2003)
Design
for test or suffer the consequences (EDN January
23, 2003)
Chip
architecture allows "testless" design flow (EE
Times September 5, 2002)
SynTest
readies scan-test data compaction tool (EE Times
September 2, 2002)
'To
BIST' or 'Not To BIST?' (EDAVision July 2002)
Debug: The Next Big Thing in DFT (Reed Electronics April 29, 2002)
Cutting SoC Test Costs with the Right Kind of Scan (EDAVision February 1, 2002)
Efficient Double Fault Diagnosis For CMOS Logic Circuits (VLSI/CAD Symposium, Taiwan, 2001)
SynTest
rolls out design-for-test software to reduce chip-testing costs
(EE Times October 30, 2001)
DFT
Takes on Test Cost in Final Combat (EE Times
October 3, 2001)
SoCs
lend momentum to design-for-test solutions (EE
Times June 5, 2001)
Logic
built-in self test needed for SoC (EE Times December
18, 2000)
The
New Testability Sins: Don't Atone, Avoid! (EE
Times March 29, 2001)
Archive
of Past SynTest Related Articles
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